Datasheet
54
4341H–MP3–10/07
AT8xC51SND2C/MP3B
Figure 11-3. Mode 0 Overflow Period Formula
11.3.2 Mode 1 (16-bit Timer)
Mode 1 configures Timer 0 as a 16-bit Timer with TH0 and TL0 registers connected in cascade
(see Figure 11-4). The selected input increments TL0 register. Figure 11-5 gives the overflow
period calculation formula when in timer mode.
Figure 11-4. Timer/Counter x (x = 0 or 1) in Mode 1
Figure 11-5. Mode 1 Overflow Period Formula
11.3.3 Mode 2 (8-bit Timer with Auto-Reload)
Mode 2 configures Timer 0 as an 8-bit Timer (TL0 register) that automatically reloads from TH0
register (see Table 11-2). TL0 overflow sets TF0 flag in TCON register and reloads TL0 with the
contents of TH0, which is preset by software. When the interrupt request is serviced, hardware
clears TF0. The reload leaves TH0 unchanged. The next reload value may be changed at any
time by writing it to TH0 register. Figure 11-7 gives the autoreload period calculation formula
when in timer mode.
Figure 11-6. Timer/Counter x (x = 0 or 1) in Mode 2
Figure 11-7. Mode 2 Autoreload Period Formula
6 ⋅
(16384 – (THx, TLx))
TFx
PER
=
F
TIMx
TRx
TCON Reg
TFx
TCON Reg
0
1
GATEx
TMOD Reg
Overflow
Timer x
Interrupt
Request
C/Tx#
TMOD Reg
TLx
(8 bits)
THx
(8 bits)
INTx
Tx
TIMx
CLOCK
÷ 6
6
⋅
(65536 – (THx, TLx))
TFx
PER
=
F
TIMx
TRx
TCON reg
TFx
TCON reg
0
1
GATEx
TMOD reg
Overflow
Timer x
Interrupt
Request
C/Tx#
TMOD reg
TLx
(8 bits)
THx
(8 bits)
INTx
Tx
TIMx
CLOCK
÷ 6
TFx
PER
=
F
TIMx
6
⋅
(256 – THx)