Datasheet
48
4341H–MP3–10/07
AT8xC51SND2C/MP3B
To determine the capacitor value to implement, the highest value of these 2 parameters has to
be chosen. Table 10-2 gives some capacitor values examples for a minimum R
RST
of 50 KΩ and
different oscillator startup and V
DD
rise times.
Table 10-2. Minimum Reset Capacitor Value for a 50 kΩ Pull-down Resistor
(1)
Note: 1. These values assume V
DD
starts from 0V to the nominal value. If the time between 2 on/off
sequences is too fast, the power-supply de-coupling capacitors may not be fully discharged,
leading to a bad reset sequence.
10.1.2 Warm Reset
To achieve a valid reset, the reset signal must be maintained for at least 2 machine cycles (24
oscillator clock periods) while the oscillator is running. The number of clock periods is mode
independent (X2 or X1).
10.1.3 Watchdog Reset
As detailed in section “Watchdog Timer”, page 60, the WDT generates a 96-clock period pulse
on the RST pin. In order to properly propagate this pulse to the rest of the application in case of
external capacitor or power-supply supervisor circuit, a 1 kΩ resistor must be added as shown in
Figure 10-2.
Figure 10-2. Reset Circuitry for WDT Reset-out Usage
10.2 Reset Recommendation to Prevent Flash Corruption
An example of bad initialization situation may occur in an instance where the bit ENBOOT in
AUXR1 register is initialized from the hardware bit BLJB upon reset. Since this bit allows map-
ping of the bootloader in the code area, a reset failure can be critical.
If one wants the ENBOOT cleared in order to unmap the boot from the code area (yet due to a
bad reset) the bit ENBOOT in SFRs may be set. If the value of Program Counter is accidently in
the range of the boot memory addresses then a Flash access (write or erase) may corrupt the
Flash on-chip memory.
It is recommended to use an external reset circuitry featuring power supply monitoring to prevent
system malfunction during periods of insufficient power supply voltage (power supply failure,
power supply switched off).
Oscillator
Start-Up Time
VDD Rise Time
1 ms 10 ms 100 ms
5 ms 820 nF 1.2 µF 12 µF
20 ms 2.7 µF 3.9 µF 12 µF
R
RST
RST
VSS
To CPU Core
and Peripherals
VDD
+
P
VDD
From WDT
Reset Source
VSS
VDD
RST
1K
To Other
On-board
Circuitry