Datasheet

44
4341H–MP3–10/07
AT8xC51SND2C/MP3B
Table 9-7. IPH1 Register
IPH1 (S:B3h) – Interrupt Priority High Register 1
Reset Value = 0000 0000b
7 6 5 4 3 2 1 0
- IPHUSB - IPHKB - IPHSPI IPHI2C IPHMMC
Bit Number
Bit
Mnemonic Description
7 -
Reserved
The value read from this bit is always 0. Do not set this bit.
6 IPHUSB
USB Interrupt Priority Level MSB
Refer to Table 9-2 for priority level description.
5 -
Reserved
The value read from this bit is always 0. Do not set this bit.
4 IPHKB
Keyboard Interrupt Priority Level MSB
Refer to Table 9-2 for priority level description.
3 IPHADC
A to D Converter Interrupt Priority Level MSB
Refer to Table 9-2 for priority level description.
2 IPHSPI
SPI Interrupt Priority Level MSB
Refer to Table 9-2 for priority level description.
1 IPHI2C
Two Wire Controller Interrupt Priority Level MSB
Refer to Table 9-2 for priority level description.
0 IPHMMC
MMC Interrupt Priority Level MSB
Refer to Table 9-2 for priority level description.