Datasheet

41
4341H–MP3–10/07
AT8xC51SND2C/MP3B
9.3 Registers
Table 9-4. IEN0 Register
IEN0 (S:A8h) – Interrupt Enable Register 0
Reset Value = 0000 0000b
7 6 5 4 3 2 1 0
EA EAUD EMP3 ES ET1 EX1 ET0 EX0
Bit Number
Bit
Mnemonic Description
7 EA
Enable All Interrupt Bit
Set to enable all interrupts.
Clear to disable all interrupts.
If EA = 1, each interrupt source is individually enabled or disabled by setting or clearing
its interrupt enable bit.
6 EAUD
Audio Interface Interrupt Enable Bit
Set to enable audio interface interrupt.
Clear to disable audio interface interrupt.
5 EMP3
MP3 Decoder Interrupt Enable Bit
Set to enable MP3 decoder interrupt.
Clear to disable MP3 decoder interrupt.
4 ES
Serial Port Interrupt Enable Bit
Set to enable serial port interrupt.
Clear to disable serial port interrupt.
3 ET1
Timer 1 Overflow Interrupt Enable Bit
Set to enable timer 1 overflow interrupt.
Clear to disable timer 1 overflow interrupt.
2 EX1
External Interrupt 1 Enable bit
Set to enable external interrupt 1.
Clear to disable external interrupt 1.
1 ET0
Timer 0 Overflow Interrupt Enable Bit
Set to enable timer 0 overflow interrupt.
Clear to disable timer 0 overflow interrupt.
0 EX0
External Interrupt 0 Enable Bit
Set to enable external interrupt 0.
Clear to disable external interrupt 0.