Datasheet

27
4341H–MP3–10/07
AT8xC51SND2C/MP3B
in standard mode or 6 oscillator clock periods in X2 mode. For further information on X2 mode,
refer to the Section “X2 Feature”, page 14.
Slow peripherals can be accessed by stretching the read and write cycles. This is done using the
M0 bit in AUXR register. Setting this bit changes the width of the RD and WR signals from 3 to
15 CPU clock periods.
For simplicity, Figure 7-4 and Figure 7-5 depict the bus cycle waveforms in idealized form and
do not provide precise timing information. For bus cycle timing parameters refer to the Section
“AC Characteristics”.
Figure 7-4. External Data Read Waveforms
Notes: 1. RD signal may be stretched using M0 bit in AUXR register.
2. When executing MOVX @Ri instruction, P2 outputs SFR content.
3. When executing MOVX @DPTR instruction, if DPHDIS is set (Page Access Mode), P2 out-
puts SFR content instead of DPH.
Figure 7-5. External Data Write Waveforms
Notes: 1. WR signal may be stretched using M0 bit in AUXR register.
2. When executing MOVX @Ri instruction, P2 outputs SFR content.
3. When executing MOVX @DPTR instruction, if DPHDIS is set (Page Access Mode), P2 out-
puts SFR content instead of DPH.
7.3 Dual Data Pointer
7.3.1 Description
The AT8xC51SND2C implement a second data pointer for speeding up code execution and
reducing code size in case of intensive usage of external memory accesses.
ALE
P0
P2
RD
(1)
DPL or Ri D7:0
DPH or P2
(2),(3)
P2
CPU Clock
ALE
P0
P2
WR
(1)
DPL or Ri D7:0
P2
CPU Clock
DPH or P2
(2),(3)