Datasheet

220
4341H–MP3–10/07
AT8xC51SND2C/MP3B
24.3.1.3 Waveforms
Figure 24-14. External Program Bus Cycle - Read Waveforms
24.3.2 External Data 8-bit Bus Cycles
24.3.2.1 Definition of Symbols
Table 24-11. External Data 8-bit Bus Cycles Timing Symbol Definitions
24.3.2.2 Timings
Test conditions: capacitive load on all pins= 50 pF.
Table 24-12. External Data 8-bit Bus Cycle - Read AC Timings
V
DD
= 2.7 to 3.3 V, T
A
= -40 to +85°C
T
PLIV
P2
P0
PSEN
ALE
T
LHLL
T
PLPH
Instruction In
A15:8
T
LLPL
A7:0
A15:8
T
AVLL
T
LLAX
T
PLAZ
D7:0
T
PXIX
T
PXIZ
D7:0
T
PXAV
Instruction In
A7:0 D7:0
Signals Conditions
A Address H High
D Data In L Low
L ALE V Valid
Q Data Out X No Longer Valid
R RD Z Floating
W WR
Symbol Parameter
Variable Clock
Standard Mode
Variable Clock
X2 Mode
UnitMin Max Min Max
T
CLCL
Clock Period 50 50 ns
T
LHLL
ALE Pulse Width 2·T
CLCL
-15 T
CLCL
-15 ns
T
AVLL
Address Valid to ALE Low T
CLCL
-20 0.5·T
CLCL
-20 ns
T
LLAX
Address hold after ALE Low T
CLCL
-20 0.5·T
CLCL
-20 ns
T
LLRL
ALE Low to RD Low 3·T
CLCL
-30 1.5·T
CLCL
-30 ns