Datasheet

22
4341H–MP3–10/07
AT8xC51SND2C/MP3B
6.6 Registers
Table 6-2. AUXR1 Register
AUXR1 (S:A2h) – Auxiliary Register 1
Reset Value = XXXX 00X0b
Note: 1. ENBOOT bit is only available in AT89C51SND2C product.
6.7 Hardware Bytes
Table 6-3. HSB Byte – Hardware Security Byte
7 6 5 4 3 2 1 0
- - ENBOOT - GF3 0 - DPS
Bit Number
Bit
Mnemonic Description
7 - 6 -
Reserved
The value read from these bits are indeterminate. Do not set these bits.
5 ENBOOT
1
Enable Boot Flash
Set this bit to map the boot Flash in the code space between at addresses F000h to
FFFFh.
Clear this bit to disable boot Flash.
4 -
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3 GF3
General Flag
This bit is a general-purpose user flag.
2 0
Always Zero
This bit is stuck to logic 0 to allow INC AUXR1 instruction without affecting GF3 flag.
1 - Reserved for Data Pointer Extension.
0 DPS
Data Pointer Select Bit
Set to select second data pointer: DPTR1.
Clear to select first data pointer: DPTR0.
7 6 5 4 3 2 1 0
X2B BLJB - - - LB2 LB1 LB0
Bit Number
Bit
Mnemonic Description
7 X2B
(1)
X2 Bit
Program this bit to start in X2 mode.
Unprogram (erase) this bit to start in standard mode.
6 BLJB
(2)
Boot Loader Jump Bit
Program this bit to execute the boot loader at address F000h on next reset.
Unprogram (erase) this bit to execute user’s application at address 0000h on next reset.
5 - 4 -
Reserved
The value read from these bits is always unprogrammed. Do not program these bits.
3 -
Reserved
The value read from this bit is always unprogrammed. Do not program this bit.
2 - 0 LB2:0
Hardware Lock Bits
Refer to for bits description.