Datasheet

219
4341H–MP3–10/07
AT8xC51SND2C/MP3B
24.3 AC Characteristics
24.3.1 External Program Bus Cycles
24.3.1.1 Definition of Symbols
Table 24-9. External Program Bus Cycles Timing Symbol Definitions
24.3.1.2 Timings
Test conditions: capacitive load on all pins= 50 pF.
Table 24-10. External Program Bus Cycle - Read AC Timings
V
DD
= 2.7 to 3.3 V, T
A
= -40 to +85°C
Signals Conditions
A Address H High
I Instruction In L Low
L ALE V Valid
P PSEN X No Longer Valid
Z Floating
Symbol Parameter
Variable Clock
Standard Mode
Variable Clock
X2 Mode
UnitMin Max Min Max
T
CLCL
Clock Period 50 50 ns
T
LHLL
ALE Pulse Width 2·T
CLCL
-15 T
CLCL
-15 ns
T
AVLL
Address Valid to ALE Low T
CLCL
-20 0.5·T
CLCL
-20 ns
T
LLAX
Address hold after ALE Low T
CLCL
-20 0.5·T
CLCL
-20 ns
T
LLIV
ALE Low to Valid Instruction 4·T
CLCL
-35 2·T
CLCL
-35 ns
T
PLPH
PSEN Pulse Width 3·T
CLCL
-25 1.5·T
CLCL
-25 ns
T
PLIV
PSEN Low to Valid Instruction 3·T
CLCL
-35 1.5·T
CLCL
-35 ns
T
PXIX
Instruction Hold After PSEN High 0 0 ns
T
PXIZ
Instruction Float After PSEN High T
CLCL
-10 0.5·T
CLCL
-10 ns
T
AVIV
Address Valid to Valid Instruction 5·T
CLCL
-35 2.5·T
CLCL
-35 ns
T
PLAZ
PSEN Low to Address Float 10 10 ns