Datasheet
209
4341H–MP3–10/07
AT8xC51SND2C/MP3B
24.2.1.1 I
DD,
I
DL
and I
PD
Test Conditions
Figure 24-1. I
DD
Test Condition, Active Mode
Figure 24-2. I
DL
Test Condition, Idle Mode
Figure 24-3. I
PD
Test Condition, Power-Down Mode
RST
TST
P0
All other pins are unconnected
VDD
VDD
VDD
I
DD
VDD
PVDD
UVDD
AUDVDD
X2
Clock Signal
VSS
X1
(NC)
VSS
PVSS
UVSS
AUDVSS
X2
VDD
Clock Signal
RST
VSS
TST
X1
P0
(NC)
I
DL
All other pins are unconnected
VSS
VDD
VSS
VDD
PVDD
UVDD
AUDVDD
PVSS
UVSS
AUDVSS
RST
MCMD
P0
All other pins are unconnected
VSS
VDD
TST
MDAT
VDD
I
PD
VDD
PVDD
UVDD
AUDVDD
X2
VSS
X1
(NC)
VSS
PVSS
UVSS
AUDVSS