Datasheet

204
4341H–MP3–10/07
AT8xC51SND2C/MP3B
23. Keyboard Interface
The AT8xC51SND2C implement a keyboard interface allowing the connection of a keypad. It is
based on one input with programmable interrupt capability on both high or low level. This input
allows exit from idle and power down modes.
23.1 Description
The keyboard interfaces with the C51 core through 2 special function registers: KBCON, the
keyboard control register (see Table 23-2); and KBSTA, the keyboard control and status register
(see Table 23-3).
An interrupt enable bit (EKB in IEN1 register) allows global enable or disable of the keyboard
interrupt (see Figure 23-1). As detailed in Figure 23-2 this keyboard input has the capability to
detect a programmable level according to KINL0 bit value in KBCON register. Level detection is
then reported in interrupt flag KINF0 in KBSTA register.
A keyboard interrupt is requested each time this flag is set. This flag can be masked by software
using KINM0 bits in KBCON register and is cleared by reading KBSTA register.
Figure 23-1. Keyboard Interface Block Diagram
Figure 23-2. Keyboard Input Circuitry
23.1.1 Power Reduction Mode
KIN0 inputs allow exit from idle and power-down modes as detailed in section “Power Manage-
ment”, page 47. To enable this feature, KPDE bit in KBSTA register must be set to logic 1.
Due to the asynchronous keypad detection in power down mode (all clocks are stopped), exit
may happen on parasitic key press. In this case, no key is detected and software must enter
power down again.
KIN0
Keyboard Interface
Interrupt Request
EKB
IEN1.4
Input Circuitry
KIN0
KINM0
KBCON.0
KINF0
KBSTA.0
KINL0
KBCON.4
0
1