Datasheet

200
4341H–MP3–10/07
AT8xC51SND2C/MP3B
Figure 22-2. Timing Diagram
22.1.1 Clock Generator
The ADC clock is generated by division of the peripheral clock (see details in section “X2 Fea-
ture”, page 14). The division factor is then given by ADCP4:0 bits in ADCLK register. Figure 22-
3 shows the ADC clock generator and its calculation formula
(1)
.
Figure 22-3. ADC Clock Generator and Symbol Caution:
Note: 1. In all cases, the ADC clock frequency may be higher than the maximum F
ADCLK
parameter
reported in the section “Analog to Digital Converter”, page 202.
2. The ADCD value of 0 is equivalent to an ADCD value of 32.
22.1.2 Channel Selection
The channel on which conversion is performed is selected by the ADCS bit in ADCON register
according to Table 2.
Table 2. ADC Channel Selection
22.1.3 Conversion Precision
The 10-bit precision conversion is achieved by stopping the CPU core activity during conversion
for limiting the digital noise induced by the core. This mode called the Pseudo-Idle mode
(1),(2)
is
enabled by setting the ADIDL bit in ADCON register
(3)
. Thus, when conversion is launched (see
Section "Conversion Launching", page 201), the CPU core is stopped until the end of the con-
ADEN
ADSST
ADEOC
T
SETUP
T
CONV
CLK
T
ADCLK
ADCD4:0
ADCLK
ADC Clock
ADCclk
PERclk
2 ADCD
-------------------------=
ADC Clock Symbol
ADC
CLOCK
PER
CLOCK
÷
2
ADCS Channel
0 AIN1
1 AIN0