Datasheet

177

4341H–MP3–10/07

AT8xC51SND2C/MP3B

20.7 Interrupt

The Serial I/O Port handles 2 interrupt sources that are the “end of reception” (RI in SCON) and

“end of transmission” (TI in SCON) flags. As shown in Figure 20-16 these flags are combined

together to appear as a single interrupt source for the C51 core. Flags must be cleared by soft-

ware when executing the serial interrupt service routine.

The serial interrupt is enabled by setting ES bit in IEN0 register. This assumes interrupts are glo-

bally enabled by setting EA bit in IEN0 register.

Depending on the selected mode and weather the framing error detection is enabled or dis-

abled, RI flag is set during the stop bit or during the ninth bit as detailed in Figure 20-17.

Figure 20-16. Serial I/O Interrupt System

Figure 20-17. Interrupt Waveforms

IEN0.4

Serial I/O

Interrupt Request

SCON.1

SCON.0

RXD D0 D1 D2 D3 D4 D5 D6 D7

Start Bit 8-bit Data Stop Bit

SMOD0 = X

SMOD0 = 1

a. Mode 1

b. Mode 2 and 3

RXD D0 D1 D2 D3 D4 D5 D6 D8

Start bit 9-bit data Stop bit

SMOD0 = 1

SMOD0 = 0