Datasheet

169
4341H–MP3–10/07
AT8xC51SND2C/MP3B
Figure 20-1. Timer 1 Baud Rate Generator Block Diagram
20.2.2 Internal Baud Rate Generator
When using the Internal Baud Rate Generator, the Baud Rate is derived from the overflow of the
timer. As shown in Figure 20-2 the Internal Baud Rate Generator is an 8-bit auto-reload timer
fed by the peripheral clock or by the peripheral clock divided by 6 depending on the SPD bit in
BDRCON register (see Table 20-7). The Internal Baud Rate Generator is enabled by setting
BBR bit in BDRCON register. SMOD1 bit in PCON register allows doubling of the generated
baud rate.
Figure 20-2. Internal Baud Rate Generator Block Diagram
20.3 Synchronous Mode (Mode 0)
Mode 0 is a half-duplex, synchronous mode, which is commonly used to expand the I/0 capabil-
ities of a device with shift registers. The transmit data (TXD) pin outputs a set of eight clock
pulses while the receive data (RXD) pin transmits or receives a Byte of data. The 8-bit data are
transmitted and received least-significant bit (LSB) first. Shifts occur at a fixed Baud Rate (see
Section "Baud Rate Selection (Mode 0)", page 171). Figure 20-3 shows the serial port block dia-
gram in Mode 0.
TR1
TCON.6
0
1
GATE1
TMOD.7
Overflow
C/T1#
TMOD.6
TL1
(8 bits)
TH1
(8 bits)
INT1
T1
PER
CLOCK
÷ 6
0
1
SMOD1
PCON.7
÷ 2
T1
CLOCK
To serial
Port
0
1
Overflow
SPD
BDRCON.1
BRG
(8 bits)
BRL
(8 bits)
PER
CLOCK
÷ 6
IBRG
CLOCK
BRR
BDRCON.4
0
1
SMOD1
PCON.7
÷ 2
To serial
Port
IBRG0
CLOCK
To serial
Port (M0)