Datasheet

160
4341H–MP3–10/07
AT8xC51SND2C/MP3B
Figure 19-7. SS Timing Diagram
19.1.6 Error Conditions
The following flags signal the SPI error conditions:
• MODF in SPSTA signals a mode fault.
MODF flag is relevant only in master mode when SS usage is enabled (SSDIS bit cleared).
It signals when set that an other master on the bus has asserted SS pin and so, may create
a conflict on the bus with 2 master sending data at the same time.
• A mode fault automatically disables the SPI (SPEN cleared) and configures the SPI in slave
mode (MSTR cleared).
MODF flag can trigger an interrupt as explained in Section "Interrupt", page 160.
MODF flag is cleared by reading SPSTA and re-configuring SPI by writing to SPCON.
• WCOL in SPSTA signals a write collision.
WCOL flag is set when SPDAT is loaded while a transfer is on-going. In this case data is not
written to SPDAT and transfer continue uninterrupted. WCOL flag does not trigger any
interrupt and is relevant jointly with SPIF flag.
WCOL flag is cleared after reading SPSTA and writing new data to SPDAT while no transfer
is on-going.
19.2 Interrupt
The SPI handles 2 interrupt sources that are the “end of transfer” and the “mode fault” flags.
As shown in Figure 19-8, these flags are combined toghether to appear as a single interrupt
source for the C51 core. The SPIF flag is set at the end of an 8-bit shift in and out and is cleared
by reading SPSTA and then reading from or writing to SPDAT.
The MODF flag is set in case of mode fault error and is cleared by reading SPSTA and then writ-
ing to SPCON.
The SPI interrupt is enabled by setting ESPI bit in IEN1 register. This assumes interrupts are
globally enabled by setting EA bit in IEN0 register.
Figure 19-8. SPI Interrupt System
19.3 Configuration
The SPI configuration is made through SPCON.
19.3.1 Master Configuration
The SPI operates in master mode when the MSTR bit in SPCON is set.
SS (CPHA = 1)
SS (CPHA = 0)
SI/SO
Byte 1 Byte 2 Byte 3
ESPI
IEN1.2
SPI Controller
Interrupt Request
SPIF
SPSTA.7
MODF
SPSTA.4