Datasheet

159
4341H–MP3–10/07
AT8xC51SND2C/MP3B
For simplicity, Figure 19-5 and Figure 19-6 depict the SPI waveforms in idealized form and do
not provide precise timing information. For timing parameters refer to the Section “AC
Characteristics”.
Note: 1. When the peripheral is disabled (SPEN = 0), default SCK line is high level.
Figure 19-5. Data Transmission Format (CPHA = 0)
Figure 19-6. Data Transmission Format (CPHA = 1)
19.1.5 SS Management
Figure 19-5 shows an SPI transmission with CPHA = 0, where the first SCK edge is the MSB
capture point. Therefore the slave starts to output its MSB as soon as it is selected: SS asserted
to low level. SS must then be deasserted between each Byte transmission (see Figure 19-7).
SPDAT must be loaded with a data before SS is asserted again.
Figure 19-6 shows an SPI transmission with CPHA = 1, where the first SCK edge is used by the
slave as a start of transmission signal. Therefore, SS may remain asserted between each Byte
transmission (see Figure 19-7).
1 2 3 4 5 6 7 8
MSB
bit 1 LSBbit 2bit 4 bit 3bit 6 bit 5
bit 1bit 2bit 4 bit 3bit 6 bit 5MSB LSB
MOSI (From Master)
MISO (From Slave)
SCK (CPOL = 1)
SCK (CPOL = 0)
SPEN (Internal)
SCK Cycle Number
SS (to slave)
Capture point
1 2 3 4 5 6 7 8
MSB bit 1 LSBbit 2bit 4 bit 3bit 6 bit 5
bit 1bit 2bit 4 bit 3bit 6 bit 5MSB LSB
MOSI (from master)
MISO (from slave)
SCK (CPOL = 1)
SCK (CPOL = 0)
SPEN (internal)
SCK cycle number
SS (to slave)
Capture point