Datasheet

158
4341H–MP3–10/07
AT8xC51SND2C/MP3B
When the AT8xC51SND2C is the only slave on the bus, it can be useful not to use SS# pin and
get it back to I/O functionality. This is achieved by setting SSDIS bit in SPCON. This bit has no
effect when CPHA is cleared (see Section "SS Management", page 159).
Figure 19-4. SPI Slave Mode Block Diagram
Note: 1. MSTR bit in SPCON is cleared to select slave mode.
19.1.3 Bit Rate
The bit rate can be selected from seven predefined bit rates using the SPR2, SPR1 and SPR0
control bits in SPCON according to Table 19-1. These bit rates are derived from the peripheral
clock (F
PER
) issued from the Clock Controller block as detailed in Section "Oscillator", page 13.
Table 19-1. Serial Bit Rates
Notes: 1. These frequencies are achieved in X1 mode, F
PER
= F
OSC
÷ 2.
2. These frequencies are achieved in X2 mode, F
PER
= F
OSC
.
19.1.4 Data Transfer
The Clock Polarity bit (CPOL in SPCON) defines the default SCK line level in idle state
(1)
while
the Clock Phase bit (CPHA in SPCON) defines the edges on which the input data are sampled
and the edges on which the output data are shifted (see Figure 19-5 and Figure 19-6). The SI
signal is output from the selected slave and the SO signal is the output from the master. The
AT8xC51SND2C captures data from the SI line while the selected slave captures data from the
SO line.
MISO/P4.2
MOSI/P4.1
SS/P4.3 SPIF
SPSTA.7
CPOL
SPCON.3
CPHA
SPCON.2
8-bit Shift Register
SPDAT WR
I Q
Internal Bus
SPDAT RD
SCK/P4.2
SSDIS
SPCON.5
Control and Clock Logic
SPR2 SPR1 SPR0
Bit Rate (kHz) Vs F
PER
F
PER
Divider6 MHz
(1)
8 MHz
(1)
10 MHz
(1)
12 MHz
(2)
16 MHz
(2)
20 MHz
(2)
0 0 0 3000 4000 5000 6000 8000 10000 2
0 0 1 1500 2000 2500 3000 4000 5000 4
0 1 0 750 1000 1250 1500 2000 2500 8
0 1 1 375 500 625 750 1000 1250 16
1 0 0 187.5 250 312.5 375 500 625 32
1 0 1 93.75 125 156.25 187.5 250 312.5 64
1 1 0 46.875 62.5 78.125 93.75 125 156.25 128
1 1 1 6000 8000 10000 12000 16000 20000 1