Datasheet

143
4341H–MP3–10/07
AT8xC51SND2C/MP3B
Figure 18-14. Data Line Controller Block Diagram
18.6.1 FIFO Implementation
The 16-Byte FIFO is based on a dual 8-Byte FIFOs managed using 2 pointers and four flags
indicating the status full and empty of each FIFO.
Pointers are not accessible to user but can be reset at any time by setting and clearing DRPTR
and DTPTR bits in MMCON0 register. Resetting the pointers is equivalent to abort the writing or
reading of data.
F1EI and F2EI flags in MMINT register signal when set that respectively FIFO1 and FIFO2 are
empty. F1FI and F2FI flags in MMINT register signal when set that respectively FIFO1 and
FIFO2 are full. These flags may generate an MMC interrupt request as detailed in
Section “Interrupt”.
18.6.2 Data Configuration
Before sending or receiving any data, the data line controller must be configured according to
the type of the data transfer considered. This is achieved using the Data Format bit: DFMT in
MMCON0 register. Clearing DFMT bit enables the data stream format while setting DFMT bit
enables the data block format. In data block format, user must also configure the single or multi-
block mode by clearing or setting the MBLOCK bit in MMCON0 register and the block length
using BLEN3:0 bits in MMCON1 according to Table 18-7. Figure 18-15 summarizes the data
modes configuration flows.
Table 18-7. Block Length Programming
MCBI
MMINT.1
DATFS
MMSTA.3
CRC16S
MMSTA.4
F2FI
MMINT.3
F2EI
MMINT.1
DFMT
MMCON0.2
MBLOCK
MMCON0.3
DATDIR
MMCON1.3
Data Converter
// -> Serial
BLEN3:0
MMCON1.7:4
DATEN
MMCON1.2
DATA Line
Finished State Machine
Data Converter
Serial -> //
DTPTR
MMCON0.6
DRPTR
MMCON0.7
TX Pointer
RX Pointer
8-Byte
FIFO 1
8-Byte
FIFO 2
16-Byte FIFO
MMDAT
F1EI
MMINT.0
CRC16 and Format
Checker
F1FI
MMINT.2
EOFI
MMINT.4
CBUSY
MMSTA.5
CRC16
Generator
MDAT
BLEN3:0 Block Length (Byte)
BLEN = 0000 to 1011 Length = 2
BLEN
: 1 to 2048
> 1011 Reserved: do not program BLEN3:0 > 1011