Datasheet

142

4341H–MP3–10/07

AT8xC51SND2C/MP3B

Figure 18-13. Command Transmission Flow

18.5.2 Command Receiver

The end of the response reception is signalled to you by the EORI flag in MMINT register. This

flag may generate an MMC interrupt request as detailed in Section "Interrupt", page 148. When

this flag is set, 2 other flags in MMSTA register: RESPFS and CRC7S give a status on the

response received. RESPFS indicates if the response format is correct or not: the size is the one

expected (48 bits or 136 bits) and a valid End bit has been received, and CRC7S indicates if the

CRC7 computation is correct or not. These Flags are cleared when a command is sent to the

card and updated when the response has been received.

User may abort response reading by setting and clearing the CRPTR bit in MMCON0 register

which resets the read pointer to the receive FIFO.

According to the MMC specification delay between a command and a response (formally N

parameter) can not exceed 64 MMC clock periods. To avoid any locking of the MMC controller

when card does not send its response (e.g. physically removed from the bus), user must launch

a time-out period to exit from such situation. In case of time-out user may reset the command

controller and its internal state machine by setting and clearing the CCR bit in MMCON2

This time-out may be disarmed when receiving the response.

18.6 Data Line Controller

The data line controller is based on a 16-Byte FIFO used both by the data transmitter channel

and by the data receiver channel.

Command

Transmission

Load Command in

Buffer

MMCMD = index

MMCMD = argument

Configure Response

RESPEN = X

RFMT = X

CRCDIS = X

Transmit Command

CMDEN = 1

CMDEN = 0