Datasheet

141
4341H–MP3–10/07
AT8xC51SND2C/MP3B
Figure 18-12. Command Line Controller Block Diagram
18.5.1 Command Transmitter
For sending a command to the card, user must load the command index (1 Byte) and argument
(4 Bytes) in the command transmit FIFO using the MMCMD register. Before starting transmis-
sion by setting and clearing the CMDEN bit in MMCON1 register, user must first configure:
• RESPEN bit in MMCON1 register to indicate whether a response is expected or not.
• RFMT bit in MMCON0 register to indicate the response size expected.
• CRCDIS bit in MMCON0 register to indicate whether the CRC7 included in the response will
be computed or not. In order to avoid CRC error, CRCDIS may be set for response that do
not include CRC7.
Figure 18-13 summarizes the command transmission flow.
As soon as command transmission is enabled, the CFLCK flag in MMSTA is set indicating that
write to the FIFO is locked. This mechanism is implemented to avoid command overrun.
The end of the command transmission is signalled to you by the EOCI flag in MMINT register
becoming set. This flag may generate an MMC interrupt request as detailed in Section "Inter-
rupt", page 148. The end of the command transmission also resets the CFLCK flag.
User may abort command loading by setting and clearing the CTPTR bit in MMCON0 register
which resets the write pointer to the transmit FIFO.
CTPTR
MMCON0.4
CRPTR
MMCON0.5
MCMD
CMDEN
MMCON1.0
TX COMMAND Line
Finished State Machine
Data Converter
// -> Serial
5-Byte FIFO
MMCMD
TX Pointer
RFMT
MMCON0.1
CRCDIS
MMCON0.0
RESPEN
MMCON1.1
Data Converter
Serial -> //
RX Pointer
17 - Byte FIFO
MMCMD
CFLCK
MMSTA.0
CRC7
Generator
RX COMMAND Line
Finished State Machine
CRC7 and Format
Checker
CRC7S
MMSTA.2
RESPFS
MMSTA.1
EOCI
MMINT.5
EORI
MMINT.6
Command Transmitter
Command Receiver
Write
Read