Datasheet

140
4341H–MP3–10/07
AT8xC51SND2C/MP3B
Figure 18-9. MMC Controller Block Diagram
18.4 Clock Generator
The MMC clock is generated by division of the oscillator clock (F
OSC
) issued from the Clock Con-
troller block as detailed in Section "Oscillator", page 13. The division factor is given by MMCD7:0
bits in MMCLK register, a value of 0x00 stops the MMC clock. Figure 18-10 shows the MMC
clock generator and its output clock calculation formula.
Figure 18-10. MMC Clock Generator and Symbol
As soon as MMCEN bit in MMCON2 is set, the MMC controller receives its system clock. The
MMC command and data clock is generated on MCLK output and sent to the command line and
data line controllers. Figure 18-11 shows the MMC controller configuration flow.
As exposed in Section “Clock Control”, page 139, MMCD7:0 bits can be used to dynamically
increase or reduce the MMC clock.
Figure 18-11. Configuration Flow
18.5 Command Line Controller
As shown in Figure 18-12, the command line controller is divided in 2 channels: the command
transmitter channel that handles the command transmission to the card through the MCMD line
and the command receiver channel that handles the response reception from the card through
the MCMD line. These channels are detailed in the following sections.
OSC
CLOCK
MCMD
MCLK
8
Internal
Bus
MDAT
Command Line
Clock
MMC
Interrupt
Request
Generator
Controller
Data Line
Controller
Interrupt
Controller
MMCD7:0
MMCLK
MMC Clock
MMCclk
OSCclk
MMCD 1+
-----------------------------=
OSC
CLOCK
MMCEN
MMCON2.7
Controller Clock
MMC
CLOCK
MMC Clock Symbol
MMC Controller
Configuration
Configure MMC Clock
MMCLK = XXh
MMCEN = 1
FLOWC = 0