Datasheet

128
4341H–MP3–10/07
AT8xC51SND2C/MP3B
Table 16-11. UEPINT Register
UEPINT (S:F8h Read-only) – USB Endpoint Interrupt Register
Reset Value = 0000 0000b
Table 16-12. UEPDATX Register
UEPDATX (S:CFh) – USB Endpoint X FIFO Data Register (X = EPNUM set in UEPNUM)
Reset Value = XXh
7 6 5 4 3 2 1 0
- - - - - EP2INT EP1INT EP0INT
Bit Number
Bit
Mnemonic Description
7 - 3 -
Reserved
The value read from these bits is always 0. Do not set these bits.
2 EP2INT
Endpoint 2 Interrupt Flag
This bit is set by hardware when an endpoint interrupt source has been detected on the
endpoint 2. The endpoint interrupt sources are in the UEPSTAX register and can be:
TXCMP, RXOUTB0, RXOUTB1, RXSETUP or STLCRC.
A USB interrupt is triggered when the EP2IE bit in the UEPIEN register is set.
This bit is cleared by hardware when all the endpoint interrupt sources are cleared.
1 EP1INT
Endpoint 1 Interrupt Flag
This bit is set by hardware when an endpoint interrupt source has been detected on the
endpoint 1. The endpoint interrupt sources are in the UEPSTAX register and can be:
TXCMP, RXOUTB0, RXOUTB1, RXSETUP or STLCRC.
A USB interrupt is triggered when the EP1IE bit in the UEPIEN register is set.
This bit is cleared by hardware when all the endpoint interrupt sources are cleared.
0 EP0INT
Endpoint 0 Interrupt Flag
This bit is set by hardware when an endpoint interrupt source has been detected on the
endpoint 0. The endpoint interrupt sources are in the UEPSTAX register and can be:
TXCMP, RXOUTB0, RXOUTB1, RXSETUP or STLCRC.
A USB interrupt is triggered when the EP0IE bit in the UEPIEN register is set.
This bit is cleared by hardware when all the endpoint interrupt sources are cleared.
7 6 5 4 3 2 1 0
FDAT7 FDAT6 FDAT5 FDAT4 FDAT3 FDAT2 FDAT1 FDAT0
Bit Number
Bit
Mnemonic Description
7 - 0 FDAT7:0
Endpoint X FIFO Data
Data Byte to be written to FIFO or data Byte to be read from the FIFO, for the Endpoint X
(see EPNUM).