Datasheet

127
4341H–MP3–10/07
AT8xC51SND2C/MP3B
Table 16-9. UEPRST Register
UEPRST (S:D5h) – USB Endpoint FIFO Reset Register
Reset Value = 0000 0000b
Table 16-10. UEPIEN Register
UEPIEN (S:C2h) – USB Endpoint Interrupt Enable Register
Reset Value = 0000 0000b
7 6 5 4 3 2 1 0
- - - - - EP2RST EP1RST EP0RST
Bit Number
Bit
Mnemonic Description
7 - 3 -
Reserved
The value read from these bits is always 0. Do not set these bits.
2 EP2RST
Endpoint 2 FIFO Reset
Set and clear to reset the endpoint 2 FIFO prior to any other operation, upon hardware
reset or when an USB bus reset has been received.
1 EP1RST
Endpoint 1 FIFO Reset
Set and clear to reset the endpoint 1 FIFO prior to any other operation, upon hardware
reset or when an USB bus reset has been received.
0 EP0RST
Endpoint 0 FIFO Reset
Set and clear to reset the endpoint 0 FIFO prior to any other operation, upon hardware
reset or when an USB bus reset has been received.
7 6 5 4 3 2 1 0
- - - - - EP2INTE EP1INTE EP0INTE
Bit Number
Bit
Mnemonic Description
7 - 3 -
Reserved
The value read from these bits is always 0. Do not set these bits.
2 EP2INTE
Endpoint 2 Interrupt Enable Bit
Set to enable the interrupts for endpoint 2.
Clear this bit to disable the interrupts for endpoint 2.
1 EP1INTE
Endpoint 1 Interrupt Enable Bit
Set to enable the interrupts for the endpoint 1.
Clear to disable the interrupts for the endpoint 1.
0 EP0INTE
Endpoint 0 Interrupt Enable Bit
Set to enable the interrupts for the endpoint 0.
Clear to disable the interrupts for the endpoint 0.