Datasheet

124
4341H–MP3–10/07
AT8xC51SND2C/MP3B
Table 16-6. USBIEN Register
USBIEN (S:BEh) – USB Global Interrupt Enable Register
Reset Value = 0001 0000b
Table 16-7. UEPNUM Register
UEPNUM (S:C7h) – USB Endpoint Number
Reset Value = 0000 0000b
7 6 5 4 3 2 1 0
- - EWUPCPU EEORINT ESOFINT - - ESPINT
Bit Number
Bit
Mnemonic Description
7 - 6 -
Reserved
The value read from these bits is always 0. Do not set these bits.
5 EWUPCPU
Wake Up CPU Interrupt Enable Bit
Set to enable the Wake Up CPU interrupt.
Clear to disable the Wake Up CPU interrupt.
4 EEOFINT
End Of Reset Interrupt Enable Bit
Set to enable the End Of Reset interrupt. This bit is set after reset.
Clear to disable End Of Reset interrupt.
3 ESOFINT
Start Of Frame Interrupt Enable Bit
Set to enable the SOF interrupt.
Clear to disable the SOF interrupt.
2 - 1 -
Reserved
The value read from these bits is always 0. Do not set these bits.
0 ESPINT
Suspend Interrupt Enable Bit
Set to enable Suspend interrupt.
Clear to disable Suspend interrupt.
7 6 5 4 3 2 1 0
- - - - - - EPNUM1 EPNUM0
Bit Number
Bit
Mnemonic Description
7 - 2 -
Reserved
The value read from these bits is always 0. Do not set these bits.
1 - 0 EPNUM1:0
Endpoint Number Bits
Set this field with the number of the endpoint which should be accessed when reading or
writing to registers UEPSTAX, UEPDATX, UBYCTX or UEPCONX.