Datasheet

12
4341H–MP3–10/07
AT8xC51SND2C/MP3B
4.4 Internal Pin Structure
Table 4-17. Detailed Internal Pin Structure
Notes: 1. For information on resistors value, input/output levels, and drive capability, refer to the
Section “DC Characteristics”, page 201.
2. When the Two Wire controller is enabled, P
3
transistors are disabled allowing pseudo open-
drain structure.
Circuit
(1)
Type Pins
Input TST
Input/Output RST
Input/Output
P3
P4
Input/Output
P0
MCMD
MDAT
ISP
PSEN
Output
ALE
SCLK
DCLK
DOUT
DSEL
MCLK
Input/Output
D+
D-
R
TST
VDD
R
RST
VSS
P
VDD
Watchdog Output
P
3
VSS
N
P
1
VDD VDD
2 osc
Latch Output
periods
P
2
VDD
VSS
N
P
VDD
VSS
N
P
VDD
D+
D-