Datasheet
113
4341H–MP3–10/07
AT8xC51SND2C/MP3B
16.6.4 Bulk/Interrupt IN Transactions in Ping-pong Mode
Figure 16-12. Bulk/Interrupt IN transactions in Ping-pong mode
An endpoint should be first enabled and configured before being able to send Bulk or Interrupt
packets.
The firmware should fill the FIFO bank 0 with the data to be sent and set the TXRDY bit in the
UEPSTAX register to allow the USB controller to send the data stored in FIFO at the next IN
request concerning the endpoint. The FIFO banks are automatically switched, and the firmware
can immediately write into the endpoint FIFO bank 1.
When the IN packet concerning the bank 0 has been sent and acknowledged by the Host, the
TXCMPL bit is set by the USB controller. This triggers a USB interrupt if enabled. The firmware
should clear the TXCMPL bit before filling the endpoint FIFO bank 0 with new data. The FIFO
banks are then automatically switched.
When the IN packet concerning the bank 1 has been sent and acknowledged by the Host, the
TXCMPL bit is set by the USB controller. This triggers a USB interrupt if enabled. The firmware
should clear the TXCMPL bit before filling the endpoint FIFO bank 1 with new data.
The bank switch is performed by the USB controller each time the TXRDY bit is set by the firm-
ware. Until the TXRDY bit has been set by the firmware for an endpoint bank, the USB controller
will answer a NAK handshake for each IN requests concerning this bank.
Note that in the example above, the firmware clears the Transmit Complete bit (TXCBulk-out-
MPL) before setting the Transmit Ready bit (TXRDY). This is done in order to avoid the firmware
to clear at the same time the TXCMPL bit for for bank 0 and the bank 1.
The firmware should never write more Bytes than supported by the endpoint FIFO.
IN
DATA0 (n Bytes)
ACK
HOST UFI
C51
Endpoint FIFO bank 0 - Write Byte 1
IN
NACK
TXCMPL
Endpoint FIFO bank 0 - Write Byte 2
Endpoint FIFO bank 0 - Write Byte n
Set TXRDY
Endpoint FIFO bank 1 - Write Byte 1
Endpoint FIFO bank 1 - Write Byte 2
Endpoint FIFO bank 1 - Write Byte m
Set TXRDY
IN
DATA1 (m Bytes)
ACK
Endpoint FIFO bank 0 - Write Byte 1
Endpoint FIFO bank 0 - Write Byte 2
Endpoint FIFO bank 0 - Write Byte p
Set TXRDY
Clear TXCMPL
IN
DATA0 (p Bytes)
ACK
TXCMPL
Clear TXCMPL
Endpoint FIFO bank 1 - Write Byte 1