Datasheet
112
4341H–MP3–10/07
AT8xC51SND2C/MP3B
If the Host sends more Bytes than supported by the endpoint FIFO, the overflow data won’t be
stored, but the USB controller will consider that the packet is valid if the CRC is correct.
16.6.3 Bulk/Interrupt IN Transactions in Standard Mode
Figure 16-11. Bulk/Interrupt IN Transactions in Standard Mode
An endpoint should be first enabled and configured before being able to send Bulk or Interrupt
packets.
The firmware should fill the FIFO with the data to be sent and set the TXRDY bit in the UEP-
STAX register to allow the USB controller to send the data stored in FIFO at the next IN request
concerning this endpoint. To send a Zero Length Packet, the firmware should set the TXRDY bit
without writing any data into the endpoint FIFO.
Until the TXRDY bit has been set by the firmware, the USB controller will answer a NAK hand-
shake for each IN requests.
To cancel the sending of this packet, the firmware has to reset the TXRDY bit. The packet stored
in the endpoint FIFO is then cleared and a new packet can be written and sent.
When the IN packet has been sent and acknowledged by the Host, the TXCMPL bit in the UEP-
STAX register is set by the USB controller. This triggers a USB interrupt if enabled. The firmware
should clear the TXCMPL bit before filling the endpoint FIFO with new data.
The firmware should never write more Bytes than supported by the endpoint FIFO.
All USB retry mechanisms are automatically managed by the USB controller.
IN
DATA0 (n Bytes)
ACK
HOST UFI
C51
Endpoint FIFO Write Byte 1
IN
NAK
TXCMPL
Endpoint FIFO Write Byte 2
Endpoint FIFO Write Byte n
Set TXRDY
Clear TXCMPL
Endpoint FIFO Write Byte 1