Datasheet

109
4341H–MP3–10/07
AT8xC51SND2C/MP3B
16.5 Read/Write Data FIFO
16.5.1 Read Data FIFO
The read access for each OUT endpoint is performed using the UEPDATX register.
After a new valid packet has been received on an Endpoint, the data are stored into the FIFO
and the Byte counter of the endpoint is updated (UBYCTX registers). The firmware has to store
the endpoint Byte counter before any access to the endpoint FIFO. The Byte counter is not
updated when reading the FIFO.
To read data from an endpoint, select the correct endpoint number in UEPNUM and read the
UEPDATX register. This action automatically decreases the corresponding address vector, and
the next data is then available in the UEPDATX register.
16.5.2 Write Data FIFO
The write access for each IN endpoint is performed using the UEPDATX register.
To write a Byte into an IN endpoint FIFO, select the correct endpoint number in UEPNUM and
write into the UEPDATX register. The corresponding address vector is automatically increased,
and another write can be carried out.
Warning 1: The Byte counter is not updated.
Warning 2: Do not write more Bytes than supported by the corresponding endpoint.
16.5.3 FIFO Mapping
Figure 16-8. Endpoint FIFO Configuration
UEPNUM
Endpoint 0
Endpoint 2
UEPSTA0 UEPCON0 UEPDAT0
UEPSTA2 UEPCON2 UEPDAT2
0
1
2
SFR Registers
UEPSTAX UEPCONX UEPDATX
X
UBYCT0
UBYCT2
UBYCTX