Datasheet

106
4341H–MP3–10/07
AT8xC51SND2C/MP3B
Figure 16-5. UFI Block Diagram
Figure 16-6. USB Typical Transaction Load
To/From C51 Core
Endpoint Control
C51 side
Endpoint Control
USB side
Endpoint 2
Endpoint 1
Endpoint 0
USBCON
USBINT
USBIEN
UEPINT
UEPIEN
UEPNUM
UEPSTAX
USBADDR
UEPCONX
UEPDATX
UEPRST
UBYCTX
UFNUMH
UFNUML
Asynchronous Information
Transfer
Control
FSM
To/From SIE
12 MHz DPLL
OUT Transactions:
HOST
UFI
C51
OUT DATA0 (n Bytes)
ACK
Endpoint FIFO read (n Bytes)
OUT DATA1
NACK
OUT DATA1
ACK
IN Transactions:
HOST
UFI
C51
IN
ACK
Endpoint FIFO Write
IN
DATA1NACK
C51 interrupt
IN
DATA1
C51 interrupt
Endpoint FIFO write