Datasheet

104
4341H–MP3–10/07
AT8xC51SND2C/MP3B
Figure 16-3 shows how to connect the AT8xC51SND2C to the USB connector. D+ and D- pins
are connected through 2 termination resistors. A pull-up resistor is implemented on D+ to inform
the host of a full speed device connection. Value of these resistors is detailed in the section “DC
Characteristics”.
Figure 16-1. USB Device Controller Block Diagram
Figure 16-2. USB Connection
16.3.1 Clock Controller
The USB controller clock is generated by division of the PLL clock. The division factor is given by
USBCD1:0 bits in USBCLK register (see Table 16-16). Figure 16-3 shows the USB controller
clock generator and its calculation formula. The USB controller clock frequency must always be
48 MHz.
Figure 16-3. USB Clock Generator and Symbol
USB
CLOCK
48 MHz 12 MHz
D+
D-
DPLL
SIE
UFI
USB
Buffer
To/From
C51 Core
D+
D-
VBUS
GND
D+
D-
VSS
To Power
R
USB
R
USB
VDD
Supply
R
FS
USBCD1:0
USBCLK
48 MHz USB Clock
USBclk
PLLclk
USBCD 1+
--------------------------------=
USB
CLOCK
USB Clock Symbol
PLL
CLOCK