Features • MPEG I/II-Layer 3 Hardwired Decoder • • • • • • • • • • • • • • • • • • • • • • – Stand-alone MP3 Decoder – 48, 44.1, 32, 24, 22.
1. Description The AT8xC51SND2C has been developed for handling MP3 ringing tones in mobile phones and can replace sound generators while adding SD/MMC card reader, MP3 music decoding, and connection of the cell phone to a PC through USB. Cell phones can also be used as a thumb drive extending cell phone capabilities.
AT8xC51SND2C/MP3B 3. Block Diagram Figure 3-1.
. Pin Description 4.1 Pinouts Figure 4-1. 10 9 8 7 6 5 4 3 2 1 NC NC P2.0/ A8 P4.1/ MOSI VDD VSS NC AUXP AUXN ALE A VDD P2.2/ A10 P2.1/ A9 P4.0/ MISO P4.2/ SCK MONON MONOP P0.0/ AD0 KIN0 ISP/ NC B P2.4/ A12 P2.3/ A11 P2.5/ A13 P4.3/ SS P0.6/ AD6 P0.4/ AD4 P0.3/ AD3 P0.2/ AD2 P0.1/ AD1 NC C P2.6/ A14 P2.7/ A15 MCLK NC P0.7/ AD7 P0.5/ AD5 NC NC NC NC D EA VSS VDD ESDVSS VDD SDA AUDVREF SCL HSL AUDVDD E MCMD MDAT NC P3.2/ INT0 P3.
AT8xC51SND2C/MP3B 4.2 Figure 4-2. 10 9 P2.2/ A10 AT8XSND2CMP3B 100-pin BGA Package (with ADC) 8 7 6 P2.1/ A9 P4.0/ MISO ESDVSS VDD VSS P2.3/ A11 P2.4/ A12 P2.0/ A8 P4.2/ SCK P0.7/ AD7 VDD P2.5/ A13 P4.1/ MOSI P4.3/ SS VSS P2.6/ A14 P2.7/ A15 VDD EA FILT MCMD MCLK MDAT AIN1 SCLK AUDRST RST AIN0 DCLK DOUT DSEL ADCV REFP VSS PAINP PAINN ADCV REFN ESDVSS AUDVSS HPP Notes: 5 4 3 2 P0.0/ AD0 1 ALE A ISP/ NC B MONON MONOP P0.5/ AD5 P0.3/ AD3 AUXP P0.
4.3 Signals All the AT8xC51SND2C and AT8XSND2CMP3B signals are detailed by functionality in Table 41 to Table 14. Table 4-1. Ports Signal Description Signal Name Type Description P0.7:0 I/O Port 0 P0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high impedance inputs. To avoid any parasitic current consumption, floating P0 inputs must be polarized to VDD or VSS. P2.
AT8xC51SND2C/MP3B Signal Name Type Description Alternate Function Timer 1 Gate Input INT1 serves as external run control for timer 1, when selected by GATE1 bit in TCON register. INT1 I T0 I Timer 0 External Clock Input When timer 0 operates as a counter, a falling edge on the T0 pin increments the count. P3.4 T1 I Timer 1 External Clock Input When timer 1 operates as a counter, a falling edge on the T1 pin increments the count. P3.5 Table 4-4.
Table 4-7. UART Signal Description Signal Name Type RXD I/O Receive Serial Data RXD sends and receives data in serial I/O mode 0 and receives data in serial I/O modes 1, 2 and 3. P3.0 TXD O Transmit Serial Data TXD outputs the shift clock in serial I/O mode 0 and transmits data in serial I/O modes 1, 2 and 3. P3.1 Table 4-8.
AT8xC51SND2C/MP3B Table 4-11. A/D Converter Signal Description (AT8XSND2CMP3B only) Signal Name Type AIN1:0 I A/D Analog Inputs - ADCREFP I Analog Positive Voltage Reference Input - ADCREFN I Analog Negative Voltage Reference Input - Table 4-12. Description Alternate Function External Access Signal Description Signal Name Type A15:8 I/O Address Lines Upper address lines for the external bus. Multiplexed higher address and data lines for the IDE interface. P2.
Table 4-14. Signal Name Type Description VDD PWR Digital Supply Voltage Connect these pins to +3V supply voltage. - VSS GND Circuit Ground Connect these pins to ground. - ADCVDD PWR Analog Supply Voltage Connect this pin to +3V supply voltage. - ADCVSS PWR Analog Ground Connect this pin to ground. - PVDD PWR PLL Supply voltage Connect this pin to +3V supply voltage. - PVSS GND PLL Circuit Ground Connect this pin to ground.
AT8xC51SND2C/MP3B Description Alternate Function Signal Name Type PAINN I Audio Amplifier Negative Input - PAINP I Audio Amplifier Positive Input - AUDRST I Audio Reset (Active Low) - MONON O Audio Negative Monaural Driver Output - MONOP O Audio Positive Monaural Driver Output - AUXP I Audio Mono Auxiliary Positive Input - AUXN I Audio Mono Auxiliary Negative Input - HSL O Audio Left Channel Headset Driver Output - HSR O Audio Right Channel Headset Driver Output - LIN
4.4 Internal Pin Structure Table 4-17. Detailed Internal Pin Structure Circuit(1) Type Pins Input TST Input/Output RST Input/Output P3 P4 RTST VDD VDD P RRST Watchdog Output VSS 2 osc periods Latch Output VDD VDD VDD P1 P2 P3 N VSS VDD P Input/Output P0 MCMD MDAT ISP N PSEN VSS ALE SCLK DCLK VDD P Output DOUT DSEL MCLK N VSS D+ Input/Output D+ D- D- Notes: 12 1.
AT8xC51SND2C/MP3B 5. Clock Controller The AT8xC51SND2C clock controller is based on an on-chip oscillator feeding an on-chip Phase Lock Loop (PLL). All internal clocks to the peripherals and CPU core are generated by this controller. 5.1 Oscillator The AT8xC51SND2C X1 and X2 pins are the input and the output of a single-stage on-chip inverter (see Figure 5-1) that can be configured with off-chip components such as a Pierce oscillator (see Figure 5-2).
5.2 X2 Feature Unlike standard C51 products that require 12 oscillator clock periods per machine cycle, the AT8xC51SND2C need only 6 oscillator clock periods per machine cycle. This feature called the “X2 feature” can be enabled using the X2 bit (1) in CKCON (see Table 5-1) and allows the AT8xC51SND2C to operate in 6 or 12 oscillator clock periods per machine cycle. As shown in Figure 5-1, both CPU and peripheral clocks are affected by this feature. Figure 5-3 shows the X2 mode switching waveforms.
AT8xC51SND2C/MP3B Figure 5-4. PLL Block Diagram and Symbol PFILT PLLCON.1 PLLEN N divider OSC CLOCK Up N6:0 PFLD CHP Vref VCO Down PLOCK PLL Clock R divider PLLCON.0 R9:0 PLL CLOCK OSCclk × ( R + 1 ) PLLclk = ----------------------------------------------N+1 PLL Clock Symbol Figure 5-5. PLL Filter Connection FILT R C2 C1 VSS 5.3.2 VSS PLL Programming The PLL is programmed using the flow shown in Figure 5-6.
5.4 Registers Table 5-1. CKCON Register CKCON (S:8Fh) – Clock Control Register 7 6 5 4 3 2 1 0 TWIX2 WDX2 - SIX2 - T1X2 T0X2 X2 Bit Number Bit Mnemonic Description 7 TWIX2 Two-Wire Clock Control Bit Set to select the oscillator clock divided by 2 as TWI clock input (X2 independent). Clear to select the peripheral clock as TWI clock input (X2 dependent). 6 WDX2 Watchdog Clock Control Bit Set to select the oscillator clock divided by 2 as watchdog clock input (X2 independent).
AT8xC51SND2C/MP3B Bit Number Bit Mnemonic 1 PLLEN PLL Enable Bit Set to enable the PLL. Clear to disable the PLL. 0 PLOCK PLL Lock Indicator Set by hardware when PLL is locked. Clear by hardware when PLL is unlocked. Description Reset Value = 0000 1000b Table 5-3. PLLNDIV Register PLLNDIV (S:EEh) – PLL N Divider Register 7 6 5 4 3 2 1 0 - N6 N5 N4 N3 N2 N1 N0 Bit Number Bit Mnemonic Description 7 - 6-0 N6:0 Reserved The value read from this bit is always 0.
6. Program/Code Memory The AT8xC51SND2C execute up to 64K Bytes of program/code memory. Figure 6-1 shows the split of internal and external program/code memory spaces depending on the product. The AT83SND2C product provides the internal program/code memory in ROM memory while the AT89C51SND2C product provides it in Flash memory. These 2 products do not allow external code memory execution. The Flash memory increases EPROM and ROM functionality by in-circuit electrical erasure and programming.
AT8xC51SND2C/MP3B 6.1 ROM Memory Architecture As shown in Figure 6-2 the AT83SND2C ROM memory is composed of one space detailed in the following paragraph. Figure 6-2. AT83SND2C Memory Architecture FFFFh 64K Bytes User ROM Memory 0000h 6.1.1 User Space This space is composed of a 64K Bytes ROM memory programmed during the manufacturing process. It contains the user’s application code. 6.
6.2.3 Hardware Security Space This space is composed of one Byte: the Hardware Security Byte (HSB see Table 6-3) divided in 2 separate nibbles. The MSN contains the X2 mode configuration bit and the Boot Loader Jump Bit as detailed in Section “Boot Memory Execution”, page 20 and can be written by software while the LSN contains the lock system level to protect the memory content against piracy as detailed in Section “Hardware Security System”, page 20 and can only be written by hardware. 6.2.
AT8xC51SND2C/MP3B 6.4.2 Hardware Condition Boot Mapping The hardware condition is based on the ISP pin. When driving this pin to low level, the chip reset sets ENBOOT and forces the reset vector to F000h instead of 0000h in order to execute the boot loader software. As shown in Figure 6-4 the hardware condition always allows in-system recovery when user’s memory has been corrupted. 6.4.3 Programmed Condition Boot Mapping The programmed condition is based on the Boot Loader Jump Bit (BLJB) in HSB.
6.6 Registers Table 6-2. AUXR1 Register AUXR1 (S:A2h) – Auxiliary Register 1 7 6 5 4 3 2 1 0 - - ENBOOT - GF3 0 - DPS Bit Number Bit Mnemonic Description 7-6 - Reserved The value read from these bits are indeterminate. Do not set these bits. 1 Enable Boot Flash Set this bit to map the boot Flash in the code space between at addresses F000h to FFFFh. Clear this bit to disable boot Flash.
AT8xC51SND2C/MP3B Reset Value = XXUU UXXX, UUUU UUUU after an hardware full chip erase. Note: 1. X2B initializes the X2 bit in CKCON during the reset phase. 2. In order to ensure boot loader activation at first power-up, AT89C51SND2C products are delivered with BLJB programmed. 3. Bits 0 to 3 (LSN) can only be programmed by hardware mode. Table 6-4.
7. Data Memory The AT8xC51SND2C provides data memory access in 2 different spaces: 1. The internal space mapped in three separate segments: – The lower 128 Bytes RAM segment – The upper 128 Bytes RAM segment – The expanded 2048 Bytes RAM segment 2. The external space. A fourth internal segment is available but dedicated to Special Function Registers, SFRs, (addresses 80h to FFh) accessible by direct addressing mode.
AT8xC51SND2C/MP3B The next 16 Bytes above the register banks form a block of bit-addressable memory space. The C51 instruction set includes a wide selection of single-bit instructions, and the 128 bits in this area can be directly addressed by these instructions. The bit addresses in this area are 00h to 7Fh. Figure 7-2. Lower 128 Bytes Internal RAM Organization 7Fh 30h 2Fh 20h 18h 10h 08h 00h 7.1.
Figure 7-3 shows the structure of the external address bus. P0 carries address A7:0 while P2 carries address A15:8. Data D7:0 is multiplexed with A7:0 on P0. Table 7-3 describes the external memory interface signals. Figure 7-3. External Data Memory Interface Structure RAM PERIPHERAL AT8xC51SND2C A15:8 P2 A15:8 ALE P0 AD7:0 Latch A7:0 A7:0 D7:0 RD WR Table 7-3. 7.2.
AT8xC51SND2C/MP3B in standard mode or 6 oscillator clock periods in X2 mode. For further information on X2 mode, refer to the Section “X2 Feature”, page 14. Slow peripherals can be accessed by stretching the read and write cycles. This is done using the M0 bit in AUXR register. Setting this bit changes the width of the RD and WR signals from 3 to 15 CPU clock periods. For simplicity, Figure 7-4 and Figure 7-5 depict the bus cycle waveforms in idealized form and do not provide precise timing information.
DPTR0 and DPTR1 are seen by the CPU as DPTR and are accessed using the SFR addresses 83h and 84h that are the DPH and DPL addresses. The DPS bit in AUXR1 register (see Table 62) is used to select whether DPTR is the data pointer 0 or the data pointer 1 (see Figure 7-6). Figure 7-6. Dual Data Pointer Implementation DPL0 0 DPL1 1 DPL DPTR0 DPS DPTR1 7.3.2 DPH0 0 DPH1 1 AUXR1.
AT8xC51SND2C/MP3B 7.4 Registers Table 7-4. PSW Register PSW (S:D0h) – Program Status Word Register 7 6 5 4 3 2 1 0 CY AC F0 RS1 RS0 OV F1 P Bit Number Bit Mnemonic Description 7 CY Carry Flag Carry out from bit 1 of ALU operands. 6 AC Auxiliary Carry Flag Carry out from bit 1 of addition operands. 5 F0 User Definable Flag 0 4-3 RS1:0 Register Bank Select Bits Refer to Table 7-1 for bits description. 2 OV Overflow Flag Overflow set by arithmetic operations.
Bit Number Bit Mnemonic 1 EXTRAM 0 AO Description External RAM Enable Bit Set to select the external XRAM when executing MOVX @Ri or MOVX @DPTR instructions. Clear to select the internal expanded RAM when executing MOVX @Ri or MOVX @DPTR instructions. ALE Output Enable Bit Set to output the ALE signal only during MOVX instructions. Clear to output the ALE signal at a constant rate of FCPU/3.
AT8xC51SND2C/MP3B 8. Special Function Registers The Special Function Registers (SFRs) of the AT8xC51SND2C derivatives fall into the categories detailed in Table 8-1 to Table . The relative addresses of these SFRs are provided together with their reset values in Table 8-19. In this table, the bit-addressable registers are identified by Note 1. Table 8-1.
Table 8-4. Interrupt SFRs (Continued) Mnemonic Add Name 7 6 5 4 3 2 1 0 IPL1 - IPLUSB - IPLKB IPLADC IPLSPI IPLI2C IPLMMC 7 6 5 4 3 2 1 0 - - - - 3 2 1 0 AUDCCL K AUDCCS KIN0 B2h Interrupt Priority Control Low 1 Table 8-5. Port SFRs Mnemonic Add Name P0 80h 8-bit Port 0 P2 A0h 8-bit Port 2 P3 B0h 8-bit Port 3 P4 C0h 4-bit Port 4 Table 8-6. Auxiliary SFRs Mnemonic Add Name AUXCON 90h Auxiliary Control Table 8-7.
AT8xC51SND2C/MP3B Table 8-9.
Table 8-12.
AT8xC51SND2C/MP3B Table 8-16.
Table 8-19.
AT8xC51SND2C/MP3B 9. Interrupt System The AT8xC51SND2C, like other control-oriented computer architectures, employ a program interrupt method. This operation branches to a subroutine and performs some service in response to the interrupt. When the subroutine completes, execution resumes at the point where the interrupt occurred. Interrupts may occur as a result of internal AT8xC51SND2C activity (e.g., timer overflow) or at the initiation of electrical signals external to the microcontroller (e.g.
Table 9-2. Priority Levels IPHxx IPLxx Priority Level 0 0 0 Lowest 0 1 1 1 0 2 1 1 3 Highest A low-priority interrupt is always interrupted by a higher priority interrupt but not by another interrupt of lower or equal priority. Higher priority interrupts are serviced before lower priority interrupts. The response to simultaneous occurrence of equal priority interrupts is determined by an internal hardware polling sequence detailed in Table 9-3.
AT8xC51SND2C/MP3B Figure 9-1. Interrupt Control System INT0 00 01 10 11 External Interrupt 0 Highest Priority Interrupts EX0 00 01 10 11 IEN0.0 Timer 0 ET0 INT1 External Interrupt 1 00 01 10 11 IEN0.1 EX1 00 01 10 11 IEN0.2 Timer 1 ET1 TXD RXD Serial Port 00 01 10 11 IEN0.3 ES MP3 Decoder 00 01 10 11 IEN0.4 EMP3 Audio Interface 00 01 10 11 IEN0.5 EAUD MCLK MDAT MCMD MMC Controller 00 01 10 11 IEN0.6 EMMC SCL SDA TWI Controller 00 01 10 11 IEN1.
9.2 9.2.1 External Interrupts INT1:0 Inputs External interrupts INT0 and INT1 (INTn, n = 0 or 1) pins may each be programmed to be leveltriggered or edge-triggered, dependent upon bits IT0 and IT1 (ITn, n = 0 or 1) in TCON register as shown in Figure 9-2. If ITn = 0, INTn is triggered by a low level at the pin. If ITn = 1, INTn is negative-edge triggered. External interrupts are enabled with bits EX0 and EX1 (EXn, n = 0 or 1) in IEN0. Events on INTn set the interrupt request flag IEn in TCON register.
AT8xC51SND2C/MP3B 9.3 Registers Table 9-4. IEN0 Register IEN0 (S:A8h) – Interrupt Enable Register 0 7 6 5 4 3 2 1 0 EA EAUD EMP3 ES ET1 EX1 ET0 EX0 Bit Number Bit Mnemonic Description 7 EA Enable All Interrupt Bit Set to enable all interrupts. Clear to disable all interrupts. If EA = 1, each interrupt source is individually enabled or disabled by setting or clearing its interrupt enable bit. 6 EAUD Audio Interface Interrupt Enable Bit Set to enable audio interface interrupt.
Table 9-5. IEN1 Register IEN1 (S:B1h) – Interrupt Enable Register 1 7 6 5 4 3 2 1 0 - EUSB - EKB - ESPI EI2C EMMC Bit Number Bit Mnemonic Description 7 - 6 EUSB 5 - 4 EKB 3 EADC A to D Converter Interrupt Enable Bit Set to enable ADC interrupt. Clear to disable ADC interrupt. 2 ESPI SPI Controller Interrupt Enable Bit Set to enable SPI interrupt. Clear to disable SPI interrupt. 1 EI2C Two Wire Controller Interrupt Enable Bit Set to enable Two Wire interrupt.
AT8xC51SND2C/MP3B Table 9-6. IPH0 Register IPH0 (S:B7h) – Interrupt Priority High Register 0 7 6 5 4 3 2 1 0 - IPHAUD IPHMP3 IPHS IPHT1 IPHX1 IPHT0 IPHX0 Bit Number Bit Mnemonic Description 7 - 6 IPHAUD Audio Interface Interrupt Priority Level MSB Refer to Table 9-2 for priority level description. 5 IPHMP3 MP3 Decoder Interrupt Priority Level MSB Refer to Table 9-2 for priority level description.
Table 9-7. IPH1 Register IPH1 (S:B3h) – Interrupt Priority High Register 1 7 6 5 4 3 2 1 0 - IPHUSB - IPHKB - IPHSPI IPHI2C IPHMMC Bit Number Bit Mnemonic Description 7 - 6 IPHUSB 5 - 4 IPHKB 3 IPHADC A to D Converter Interrupt Priority Level MSB Refer to Table 9-2 for priority level description. 2 IPHSPI SPI Interrupt Priority Level MSB Refer to Table 9-2 for priority level description.
AT8xC51SND2C/MP3B Table 9-8. IPL0 Register IPL0 (S:B8h) - Interrupt Priority Low Register 0 7 6 5 4 3 2 1 0 - IPLAUD IPLMP3 IPLS IPLT1 IPLX1 IPLT0 IPLX0 Bit Number Bit Mnemonic Description 7 - 6 IPLAUD Audio Interface Interrupt Priority Level LSB Refer to Table 9-2 for priority level description. 5 IPLMP3 MP3 Decoder Interrupt Priority Level LSB Refer to Table 9-2 for priority level description.
Table 9-9. IPL1 Register IPL1 (S:B2h) – Interrupt Priority Low Register 1 7 6 5 4 3 2 1 0 - IPLUSB - IPLKB - IPLSPI IPLI2C IPLMMC Bit Number Bit Mnemonic Description 7 - 6 IPLUSB 5 - 4 IPLKB 3 IPLADC A to D Converter Interrupt Priority Level LSB Refer to Table 9-2 for priority level description. 2 IPLSPI SPI Interrupt Priority Level LSB Refer to Table 9-2 for priority level description.
AT8xC51SND2C/MP3B 10. Power Management 2 power reduction modes are implemented in the AT8xC51SND2C: the Idle mode and the Power-down mode. These modes are detailed in the following sections. In addition to these power reduction modes, the clocks of the core and peripherals can be dynamically divided by 2 using the X2 mode detailed in section “X2 Feature”, page 14. 10.
To determine the capacitor value to implement, the highest value of these 2 parameters has to be chosen. Table 10-2 gives some capacitor values examples for a minimum RRST of 50 KΩ and different oscillator startup and VDD rise times. Minimum Reset Capacitor Value for a 50 kΩ Pull-down Resistor(1) Table 10-2. Note: 10.1.2 VDD Rise Time Oscillator Start-Up Time 1 ms 10 ms 100 ms 5 ms 820 nF 1.2 µF 12 µF 20 ms 2.7 µF 3.9 µF 12 µF 1. These values assume VDD starts from 0V to the nominal value.
AT8xC51SND2C/MP3B 10.3 Idle Mode Idle mode is a power reduction mode that reduces the power consumption. In this mode, program execution halts. Idle mode freezes the clock to the CPU at known states while the peripherals continue to be clocked (refer to section “Oscillator”, page 13). The CPU status before entering Idle mode is preserved, i.e., the program counter and program status word register retain their data for the duration of Idle mode. The contents of the SFRs and RAM are also retained.
10.4.1 Entering Power-down Mode To enter Power-down mode, set PD bit in PCON register. The AT8xC51SND2C enters the Power-down mode upon execution of the instruction that sets PD bit. The instruction that sets PD bit is the last instruction executed. 10.4.2 Exiting Power-down Mode If VDD was reduced during the Power-down mode, do not exit Power-down mode until VDD is restored to the normal operating level. There are 2 ways to exit the Power-down mode: 1. Generate an enabled external interrupt.
AT8xC51SND2C/MP3B – A logic high on the RST pin clears PD bit in PCON register directly and asynchronously. This starts the oscillator and restores the clock to the CPU and peripherals. Program execution momentarily resumes with the instruction immediately following the instruction that activated Power-down mode and may continue for a number of clock cycles before the internal reset algorithm takes control. Reset initializes the AT8xC51SND2C and vectors the CPU to address 0000h. Notes: 10.5 1.
11. Timers/Counters The AT8xC51SND2C implement 2 general-purpose, 16-bit Timers/Counters. They are identified as Timer 0 and Timer 1, and can be independently configured to operate in a variety of modes as a Timer or as an event Counter. When operating as a Timer, the Timer/Counter runs for a programmed length of time, then issues an interrupt request. When operating as a Counter, the Timer/Counter counts negative transitions on an external pin.
AT8xC51SND2C/MP3B Figure 11-1. Timer 0 and Timer 1 Clock Controller and Symbols PER CLOCK 0 Timer 0 Clock PER CLOCK 0 Timer 1 Clock 1 OSC CLOCK 1 OSC CLOCK ÷2 T0X2 T1X2 CKCON.1 CKCON.2 TIM0 CLOCK TIM1 CLOCK Timer 0 Clock Symbol 11.3 ÷2 Timer 1 Clock Symbol Timer 0 Timer 0 functions as either a Timer or event Counter in four modes of operation. Figure 11-2 through Figure 11-8 show the logical configuration of each mode.
Figure 11-3. Mode 0 Overflow Period Formula TFxPER= 11.3.2 6 ⋅ (16384 – (THx, TLx)) FTIMx Mode 1 (16-bit Timer) Mode 1 configures Timer 0 as a 16-bit Timer with TH0 and TL0 registers connected in cascade (see Figure 11-4). The selected input increments TL0 register. Figure 11-5 gives the overflow period calculation formula when in timer mode. Figure 11-4.
AT8xC51SND2C/MP3B 11.3.4 Mode 3 (2 8-bit Timers) Mode 3 configures Timer 0 such that registers TL0 and TH0 operate as separate 8-bit Timers (see Figure 11-8). This mode is provided for applications requiring an additional 8-bit Timer or Counter. TL0 uses the Timer 0 control bits C/T0# and GATE0 in TMOD register, and TR0 and TF0 in TCON register in the normal manner. TH0 is locked into a Timer function (counting FTF1/6) and takes over use of the Timer 1 interrupt (TF1) and run control (TR1) bits.
11.4.1 • When Timer 0 is in mode 3, it uses Timer 1’s overflow flag (TF1) and run control bit (TR1). For this situation, use Timer 1 only for applications that do not require an interrupt (such as a Baud Rate Generator for the Serial Port) and switch Timer 1 in and out of mode 3 to turn it off and on. • It is important to stop the Timer/Counter before changing modes.
AT8xC51SND2C/MP3B 11.6 Registers Table 11-1. TCON Register TCON (S:88h) – Timer/Counter Control Register 7 6 5 4 3 2 1 0 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 Bit Number Bit Mnemonic Description 7 TF1 Timer 1 Overflow Flag Cleared by hardware when processor vectors to interrupt routine. Set by hardware on Timer/Counter overflow, when Timer 1 register overflows. 6 TR1 Timer 1 Run Control Bit Clear to turn off Timer/Counter 1. Set to turn on Timer/Counter 1.
7 6 5 4 3 2 1 0 GATE1 C/T1# M11 M01 GATE0 C/T0# M10 M00 Bit Number Bit Mnemonic 7 GATE1 Timer 1 Gating Control Bit Clear to enable Timer 1 whenever TR1 bit is set. Set to enable Timer 1 only while INT1 pin is high and TR1 bit is set. 6 C/T1# Timer 1 Counter/Timer Select Bit Clear for Timer operation: Timer 1 counts the divided-down system clock. Set for Counter operation: Timer 1 counts negative transitions on external pin T1.
AT8xC51SND2C/MP3B TL0 (S:8Ah) – Timer 0 Low Byte Register 7 6 5 4 3 2 1 0 - - - - - - - - Bit Number Bit Mnemonic Description Low Byte of Timer 0 7:0 Reset Value = 0000 0000b Table 11-4. TH1 Register TH1 (S:8Dh) – Timer 1 High Byte Register 7 6 5 4 3 2 1 0 - - - - - - - - Bit Number Bit Mnemonic Description High Byte of Timer 1 7:0 Reset Value = 0000 0000b Table 11-5.
12. Watchdog Timer The AT8xC51SND2C implement a hardware Watchdog Timer (WDT) that automatically resets the chip if it is allowed to time out. The WDT provides a means of recovering from routines that do not complete successfully due to software or hardware malfunctions. 12.1 Description The WDT consists of a 14-bit prescaler followed by a 7-bit programmable counter. As shown in Figure 12-1, the 14-bit prescaler is fed by the WDT clock detailed in Section “Watchdog Clock Controller”, page 60.
AT8xC51SND2C/MP3B 12.3 Watchdog Operation After reset, the WDT is disabled. The WDT is enabled by writing the sequence 1Eh and E1h into the WDTRST register. As soon as it is enabled, there is no way except the chip reset to disable it. If it is not cleared using the previous sequence, the WDT overflows and forces a chip reset. This overflow generates a high level 96 oscillator periods pulse on the RST pin to globally reset the application (refer to Section “Power Management”, page 47).
12.4 Registers Table 12-2. WDTRST Register WDTRST (S:A6h Write only) – Watchdog Timer Reset Register 7 6 5 4 3 2 1 0 - - - - - - - - Bit Number Bit Mnemonic Description 7-0 - Watchdog Control Value Reset Value = XXXX XXXXb Figure 12-4. WDTPRG Register WDTPRG (S:A7h) – Watchdog Timer Program Register 7 6 5 4 3 2 1 0 - - - - - WTO2 WTO1 WTO0 Bit Number Bit Mnemonic Description 7-3 - 2-0 WTO2:0 Reserved The value read from these bits is indeterminate.
AT8xC51SND2C/MP3B 13. MP3 Decoder The AT8xC51SND2C implement a MPEG I/II audio layer 3 decoder better known as MP3 decoder. In MPEG I (ISO 11172-3) three layers of compression have been standardized supporting three sampling frequencies: 48, 44.1, and 32 kHz. Among these layers, layer 3 allows highest compression rate of about 12:1 while still maintaining CD audio quality. For example, 3 minutes of CD audio (16-bit PCM, 44.1 kHz) data, which needs about 32M bytes of storage, can be encoded into only 2.
13.1.2 MP3 Data The MP3 decoder does not start any frame decoding before having a complete frame in its input buffer(1). In order to manage the load of MP3 data in the frame buffer, a hardware handshake consisting of data request and data acknowledgment is implemented. Each time the MP3 decoder needs MP3 data, it sets the MPREQ, MPFREQ and MPBREQ flags respectively in MP3STA and MP3STA1 registers. MPREQ flag can generate an interrupt if enabled as explained in Section “Interrupt”.
AT8xC51SND2C/MP3B 13.2 13.2.1 Audio Controls Volume Control The MP3 decoder implements volume control on both right and left channels. The MP3VOR and MP3VOL registers allow a 32-step volume control according to Table 13-2. Table 13-2. 13.2.2 Volume Control VOL4:0 or VOR4:0 Volume Gain (dB) 00000 Mute 00001 -33 00010 -27 11110 -1.
13.3.3 CRC Error When the CRC of a frame does not match the one calculated, the flag ERRCRC in MP3STA is set. In this case, depending on the CRCEN bit in MP3CON, the frame is played or rejected. In both cases, noise may appear at audio output. 13.4 Frame Information The MP3 frame header contains information on the audio data contained in the frame. These informations is made available in the MP3STA register for you information.
AT8xC51SND2C/MP3B All interrupt flags but MPANC are cleared when reading MP3STA register. The MPANC flag is cleared by hardware when the ancillary buffer becomes empty.. Figure 13-5. MP3 Decoder Interrupt System MPANC MP3STA.7 MSKANC MP3CON.4 MPREQ MP3STA.6 MSKREQ ERRLAY MP3 Decoder Interrupt Request MP3CON.3 MP3STA.5 ERRSYN MSKLAY EMP3 MP3CON.2 IEN0.5 MP3STA.4 MSKSYN ERRCRC MP3CON.1 MP3STA.3 MSKCRC MP3CON.
13.6.2 Management Reading the MP3STA register automatically clears the interrupt flags (acknowledgment) except the MPANC flags. This implies that register content must be saved and tested, interrupt flag by interrupt flag to be sure not to forget any interrupts. Figure 13-6.
AT8xC51SND2C/MP3B 13.7 Registers Table 13-5. MP3CON Register MP3CON (S:AAh) – MP3 Decoder Control Register 7 6 5 4 3 2 1 0 MPEN MPBBST CRCEN MSKANC MSKREQ MSKLAY MSKSYN MSKCRC Bit Number Bit Mnemonic Description 7 MPEN 6 MPBBST Bass Boost Bit Set to enable the bass boost sound effect. Clear to disable the bass boost sound effect. 5 CRCEN CRC Check Enable Bit Set to enable processing of frame that contains CRC error. Frame is played whatever the error.
Table 13-6. MP3STA Register MP3STA (S:C8h Read Only) – MP3 Decoder Status Register 7 6 5 4 3 2 1 0 MPANC MPREQ ERRLAY ERRSYN ERRCRC MPFS1 MPFS0 MPVER Bit Number Bit Mnemonic Description 7 MPANC Ancillary Data Available Flag Set by hardware as soon as one ancillary data is available (buffer not empty). Cleared by hardware when no more ancillary data is available (buffer empty). 6 MPREQ MP3 Data Request Flag Set by hardware when MP3 decoder request data. Cleared when reading MP3STA.
AT8xC51SND2C/MP3B Table 13-8. MP3STA1 Register MP3STA1 (S:AFh) – MP3 Decoder Status Register 1 7 6 5 4 3 2 1 0 - - - MPFREQ MPFREQ - - - Bit Number Bit Mnemonic Description 7-5 - 4 MPFREQ MP3 Frame Data Request Flag Set by hardware when MP3 decoder request data. Cleared when MP3 decoder no more request data . 3 MPBREQ MP3 Byte Data Request Flag Set by hardware when MP3 decoder request data. Cleared when writing to MP3DAT.
Table 13-11. MP3VOR Register MP3VOR (S:9Fh) – MP3 Volume Right Control Register 7 6 5 4 3 2 1 0 - - - VOR4 VOR3 VOR2 VOR1 VOR0 Bit Number Bit Mnemonic Description 7-5 - 4-0 VOR4:0 Reserved The value read from these bits is always 0. Do not set these bits. Volume Right Value Refer to Table 13-2 for the right channel volume control description. Reset Value = 0000 0000b Table 13-12.
AT8xC51SND2C/MP3B Table 13-14. MP3TRE Register MP3TRE (S:B6h) – MP3 Treble Control Register 7 6 5 4 3 2 1 0 - - - TRE4 TRE3 TRE2 TRE1 TRE0 Bit Number Bit Mnemonic Description 7-5 - 4-0 TRE4:0 Reserved The value read from these bits is always 0. Do not set these bits. Treble Gain Value Refer to Table 13-3 for the treble control description. Reset Value = 0000 0000b Table 13-15.
14. Audio Output Interface The AT8xC51SND2C implement an audio output interface allowing the audio bitstream to be output in various formats. It is compatible with right and left justification PCM and I2S formats and thanks to the on-chip PLL (see Section “Clock Controller”, page 13) allows connection of almost all of the commercial audio DAC families available on the market. The audio bitstream can be from 2 different types: 14.1 • The MP3 decoded bitstream coming from the MP3 decoder for playing songs.
AT8xC51SND2C/MP3B 14.2 Clock Generator The audio interface clock is generated by division of the PLL clock. The division factor is given by AUCD4:0 bits in CLKAUD register. Figure 14-2 shows the audio interface clock generator and its calculation formula. The audio interface clock frequency depends on the incoming MP3 frames and the audio DAC used. Figure 14-2.
Figure 14-4. Audio Output Format DSEL DCLK DOUT Left Channel 1 2 3 Right Channel 13 14 15 LSB MSB B14 16 B1 1 2 3 13 14 15 LSB MSB B14 16 B1 I2S Format with DSIZ = 0 and JUST4:0 = 00001. DSEL DCLK Left Channel 1 DOUT 2 Right Channel 3 17 MSB B14 LSB 18 32 1 2 3 17 MSB B14 LSB 18 32 I2S Format with DSIZ = 1 and JUST4:0 = 00001.
AT8xC51SND2C/MP3B Table 14-2. 14.5 Sample Duplication Factor DUP1 DUP0 Factor 0 0 No sample duplication, DAC rate = 8 kHz (C51 rate). 0 1 One sample duplication, DAC rate = 16 kHz (2 x C51 rate). 1 0 2 samples duplication, DAC rate = 32 kHz (4 x C51 rate). 1 1 Three samples duplication, DAC rate = 48 kHz (6 x C51 rate). MP3 Buffer In song playing mode, the audio stream comes from the MP3 decoder through a buffer.
Figure 14-6. MP3 Mode Audio Configuration Flow MP3 Mode Configuration Program Audio Clock Configure Interface HLR = X DSIZ = X POL = X JUST4:0 = XXXXXb SRC = 0 14.8 Enable DAC System Clock AUDEN = 1 Wait For DAC Set-up Time Enable Data Request DRQEN = 1 Registers Table 14-3.
AT8xC51SND2C/MP3B Bit Number Bit Mnemonic 6 DRQEN MP3 Decoded Data Request Enable Bit Set to enable data request to the MP3 decoder and to start playing song. Clear to disable data request to the MP3 decoder. 5 MSREQ Audio Sample Request Flag Mask Bit Set to prevent the SREQ flag from generating an audio interrupt. Clear to allow the SREQ flag to generate an audio interrupt. 4 MUDRN Audio Sample Under-run Flag Mask Bit Set to prevent the UDRN flag from generating an audio interrupt.
Table 14-6. AUDDAT Register AUDDAT (S:9Dh) – Audio Interface Data Register 7 6 5 4 3 2 1 0 AUD7 AUD6 AUD5 AUD4 AUD3 AUD2 AUD1 AUD0 Bit Number Bit Mnemonic Description 7-0 AUD7:0 Audio Data 8-bit sampling data for voice or sound playing. Reset Value = 1111 1111b Table 14-7.
AT8xC51SND2C/MP3B 15. DAC and PA Interface The AT8xC51SND2C implements a stereo Audio Digital-to-Analog Converter and Audio Power Amplifier targeted for Li-Ion or Ni-Mh battery powered devices. Figure 15-1. Audio Interface Block Diagram MP3 Decoder Unit DOUT DCLK DSEL I2S/PCM Audio Interface HSR HSL AUXP AUXN Audio DAC LINEL LINER MONOP MONON PAINP PAINN HPP HPN 15.
15.1.1 DAC Features • • • • • • • • 20 bit D/A Conversion 72dB Dynamic Range, -75dB THD Stereo line-in or microphone interface with 20dB amplification 93dB Dynamic Range, -80dB THD Stereo D/A conversion 74dB Dynamic Range / -65dB THD for 20mW output power over 32 Ohm loads Stereo, Mono and Reverse Stereo Mixer Left/Right speaker short-circuit detection flag Differential mono auxiliary input amplifier and PA driver Audio sampling rates (Fs): 16, 22.05, 24, 32, 44.1 and 48 kHz. Figure 15-2.
AT8xC51SND2C/MP3B 15.1.2 15.1.2.1 Digital Signals Timing Data Interface To avoid noises at the output, the reset state is maintained until proper synchronism is achieved in the DAC serial interface: • DSEL • SCLK • DCLK • DOUT The data interface allows three different data transfer modes: Figure 15-3. 20 bit I2S justified mode SCLK DSEL DOUT R1 R0 L(N-1) L(N-2) L(N-3) ... L2 L1 L0 R(N-1) R(N-2) R(N-3) ... R2 R1 R0 ... L2 L1 L0 R(N-1) R(N-2) R(N-3) ...
15.1.3 Serial Audio DAC Interface The serial audio DAC interface is a Synchronous Peripheral Interface (SPI) in slave mode: • AUDCDIN: is used to transfer data in series from the master to the slave DAC. It is driven by the master. • AUDCDOUT: is used to transfer data in series from the slave DAC to the master. It is driven by the selected slave DAC. • Serial Clock (AUDCCLK): it is used to synchronize the data transmission both in and out the devices through the AUDCDIN and AUDCDOUT lines.
AT8xC51SND2C/MP3B Figure 15-7. Dac SPI Interface AUDCCS AUDCCLK AUDCDIN rw a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 AUDCDOUT 15.1.4 DAC Interface SPI Protocol On AUDCDIN, the first bit is a read/write bit. 0 indicates a write operation while 1 is for a read operation. The 7 following bits are used for the register address and the 8 last ones are the write data. For both address and data, the most significant bit is the first one.
Table 15-1. 15.1.5 15.1.
AT8xC51SND2C/MP3B Table 15-3. Line-in gain LLIG 4:0 Table 15-4. RLIG 4:0 Gain (dB) 00000 20 00001 12 00010 9 00011 6 00100 3 00101 0 00110 -3 00111 -6 01000 -9 01001 -12 01010 -15 01011 -18 01100 -21 01101 -24 01110 -27 01111 -30 10000 -33 10001 < -60 Master Playback Gain LMPG 5:0 RMPG 5:0 Gain (dB) 000000 12.0 000001 10.5 000010 9.0 000011 7.5 000100 6.0 000101 4.5 000110 3.0 000111 1.5 001000 0.0 001001 -1.5 001010 -3.
Table 15-4. Master Playback Gain (Continued) LMPG 5:0 Table 15-5. RMPG 5:0 Gain (dB) 001011 -4.5 001100 -6.0 001101 -7.5 001110 -9.0 001111 -10.5 010000 -12.0 010001 -13.5 010010 -15.0 010011 -16.5 010100 -18.0 010101 -19.5 010110 -21.0 010111 -22.5 011000 -24.0 011001 -25.5 011010 -27.0 011011 -28.5 011100 -30.0 011101 -31.5 011110 -33.0 011111 -34.5 100000 mute Line-out Gain LLOG 5:0 88 RLOG 5:0 Gain (dB) 000000 0.0 000001 -1.5 000010 -3.
AT8xC51SND2C/MP3B Table 15-5. Table 15-6. Line-out Gain (Continued) 001000 -12.0 001001 -13.5 001010 -15.0 001011 -16.5 001100 -18.0 001101 -19.5 001110 -21.0 001111 -22.5 010000 -24.0 010001 -25.5 010010 -27.0 010011 -28.5 010100 -30.0 010101 -31.5 010110 -33.0 010111 -34.5 011000 -36.0 011001 -37.5 011010 -39.0 011011 -40.5 011100 -42.0 011101 -43.5 011110 -45.0 011111 -46.
15.1.7 Digital Mixer Control The Audio DAC features a digital mixer that allows the mixing and selection of multiple input sources. The mixing / multiplexing functions are described in the following table according with the next figure: Figure 15-9.
AT8xC51SND2C/MP3B The selection between modes is done using DINTSEL 1:0 in DAC_MISC register (refer to Table 15-22.) according to Table 15-9. Table 15-9. Format Selection 15.1.9 DINTSEL 1:0 Format 00 I2S Justified 01 MSB Justified 1x LSB Justified De-emphasis and dither enable The circuit features a de-emphasis filter for the playback channel. To enable the de-emphasis filtering, DEEMPEN must be set to high.
15.1.10 Register Table 15-11. AUXCON Register AUXCON (S:90h) – Auxiliary Control Register 7 6 5 4 3 2 1 0 SDA SCL - AUDCDOUT AUDCDIN AUDCCLK AUDCCS KIN0 Bit Number Bit Mnemonic 7 SDA Description TWI Serial Data SDA is the bidirectional Two Wire data line. TWI Serial Clock When TWI controller is in master mode, SCL outputs the serial clock to the slave peripherals. When TWI controller is in slave mode, SCL receives clock from the master controller.
AT8xC51SND2C/MP3B 0 Left channel line in amplifier ONLNIL Clear to power down. Set to power up. Reset Value = 00000000b Table 15-13. DAC Left Line In Gain Register - DAC_LLIG (01h) 7 6 5 4 3 2 1 0 - - - LLIG4 LLIG3 LLIG2 LLIG1 LLIG0 Bit Bit Number Mnemonic 7:5 - 4:0 LLIG 4:0 Description Not used Left channel line in analog gain selector Reset Value = 00000101b Table 15-14.
Table 15-16. DAC Right Master Playback Gain Register - DAC_RMPG (04h) 7 6 5 4 3 2 1 0 - - RMPG5 RMPG4 RMPG3 RMPG2 RMPG1 RMPG0 Bit Number Description Bit Mnemonic 7:6 - Not used 5:0 RMPG 5:0 Right channel master playback digital gain selector Reset Value = 00001000b Table 15-17.
AT8xC51SND2C/MP3B Table 15-19.
Table 15-21. DAC Mixer Control Register - DAC_CSFC (09h) 7 6 5 4 3 2 1 0 - - - OVRSEL - - - - Bit Bit Mnemonic Description 7:5 - Not used 4 OVRSEL Number Master clock selector Clear for 256 x Fs. Set for 384 x Fs. 3:0 - Not Used Reset Value = 00000000b Table 15-22.
AT8xC51SND2C/MP3B Table 15-23. DAC Precharge Control Register - DAC_ PRECH (0Ch) 7 6 5 4 3 2 1 PRCHARGE PRCHARGE PRCHARGE PRCHARGE PRCHARGE PRCHARGE PRCHARGE PADRV LNOL LNIL LNIL AUXIN LNOR Bit Bit Number Mnemonic 7 PRCHARGEPADR V 6 PRCHARGEAUXIN 5 PRCHARGELNOR 4 PRCHARGELNOL 3 PRCHARGELNIR 2 PRCHARGELNIL 1 PRCHARGE 0 ONMSTR 0 ONMSTR Description Differential mono PA driver pre-charge. Set to charge. Differential mono auxiliary input pre-charge. Set to charge.
Table 15-25. DAC Reset Register - DAC_ RST (10h) 7 6 5 4 3 2 1 0 - - - - - RESMASK RESFILZ RSTZ Bit Number Description Bit Mnemonic 7:3 - 2 RESMASK 1 RESFILZ 0 RSTZ Not Used. Active high reset mask of the audio codec Active low reset of the audio codec filter Active low reset of the audio codec Reset Value = 00000000b Note: 15.2 Refer to Audio DAC Startup sequence. Power Amplifier High quality mono output is provided.
AT8xC51SND2C/MP3B 0110 5 0111 2 1000 -1 1001 -4 1010 -7 1011 -10 1100 -13 1101 -16 1110 -19 1111 -22 Table 15-27. PA Operating Mode APAON APAPRECH Operating Mode 0 0 Stand-By 0 1 Input Capacitors Precharge 1 0 Active Mode 1 1 Forbidden State Table 15-28. PA Low Power Mode APALP 15.3 Power Mode 0 Low power mode 1 High power mode Audio Supplies and Start-up In operating mode AUDVBAT (supply of the audio power amplifier) must be between 3.2V and 5,5V.
15.3.1 Audio DAC Start-up Sequence In order to minimize any audio output noise during the start-up, the following sequence should be applied. 15.3.1.1 15.3.1.2 15.3.1.3 15.3.1.4 15.3.2 15.3.2.1 Example of power-on: Path DAC to Headset Output • Desassert the Reset: write 07h at address 10h. • All precharge and Master on: write FFh at address 0Ch. • Line Out On: write 30h at address 00h. • Delay 500 ms. • Precharge off: write 0Ch at address 01h. • Delay 1 ms.
AT8xC51SND2C/MP3B 15.3.3 Precharge Control The power up of the circuit can be performed independently for several blocks. The sequence flow starts by setting to High the block specific fastcharge control bit and subsequently the associated power control bit. Once the power control bit is set to High, the fast charging starts. This action begins a user controlled fastcharge cycle. When the fastcharge period is over, the user must reset the associated fastcharge bit and the block is ready for use.
15.3.4 Register Table 15-30.
AT8xC51SND2C/MP3B 16. Universal Serial Bus The AT8xC51SND2C implements a USB device controller supporting full speed data transfer. In addition to the default control endpoint 0, it provides 2 other endpoints, which can be configured in control, bulk, interrupt or isochronous modes: • Endpoint 0: 32-Byte FIFO, default control endpoint • Endpoint 1, 2: 64-Byte Ping-pong FIFO, This allows the firmware to be developed conforming to most USB device classes, for example: 16.
Figure 16-3 shows how to connect the AT8xC51SND2C to the USB connector. D+ and D- pins are connected through 2 termination resistors. A pull-up resistor is implemented on D+ to inform the host of a full speed device connection. Value of these resistors is detailed in the section “DC Characteristics”. Figure 16-1. USB Device Controller Block Diagram USB CLOCK D+ D- 48 MHz 12 MHz DPLL USB Buffer UFI To/From C51 Core SIE Figure 16-2.
AT8xC51SND2C/MP3B 16.3.2 Serial Interface Engine (SIE) The SIE performs the following functions: • NRZI data encoding and decoding. • Bit stuffing and unstuffing. • CRC generation and checking. • ACKs and NACKs automatic generation. • TOKEN type identifying. • Address checking. • Clock recovery (using DPLL). Figure 16-4.
Figure 16-5. UFI Block Diagram 12 MHz DPLL Transfer Control FSM To/From SIE Endpoint Control USB side Asynchronous Information Endpoint 2 USBCON USBADDR USBINT USBIEN UEPNUM UEPCONX UEPSTAX UEPRST UEPINT UEPIEN UEPDATX UBYCTX UFNUMH UFNUML To/From C51 Core Endpoint Control C51 side Endpoint 1 Endpoint 0 Figure 16-6.
AT8xC51SND2C/MP3B 16.4 16.4.1 Configuration General Configuration • USB controller enable Before any USB transaction, the 48 MHz required by the USB controller must be correctly generated (See “Clock Controller” on page 19). The USB controller should be then enabled by setting the EUSB bit in the USBCON register. • Set address After a Reset or a USB reset, the software has to set the FEN (Function Enable) bit in the USBADDR register.
An endpoint which is not enabled won’t answer to any USB request. The Default Control Endpoint (Endpoint 0) should always be enabled in order to answer to USB standard requests. • Endpoint type configuration All Standard Endpoints can be configured in Control, Bulk, Interrupt or Isochronous mode. The Ping-pong Endpoints can be configured in Bulk, Interrupt or Isochronous mode.
AT8xC51SND2C/MP3B 16.5 16.5.1 Read/Write Data FIFO Read Data FIFO The read access for each OUT endpoint is performed using the UEPDATX register. After a new valid packet has been received on an Endpoint, the data are stored into the FIFO and the Byte counter of the endpoint is updated (UBYCTX registers). The firmware has to store the endpoint Byte counter before any access to the endpoint FIFO. The Byte counter is not updated when reading the FIFO.
16.6 Bulk/Interrupt Transactions Bulk and Interrupt transactions are managed in the same way. 16.6.1 Bulk/Interrupt OUT Transactions in Standard Mode Figure 16-9.
AT8xC51SND2C/MP3B 16.6.2 Bulk/Interrupt OUT Transactions in Ping-pong Mode Figure 16-10.
If the Host sends more Bytes than supported by the endpoint FIFO, the overflow data won’t be stored, but the USB controller will consider that the packet is valid if the CRC is correct. 16.6.3 Bulk/Interrupt IN Transactions in Standard Mode Figure 16-11.
AT8xC51SND2C/MP3B 16.6.4 Bulk/Interrupt IN Transactions in Ping-pong Mode Figure 16-12.
16.7 16.7.1 Control Transactions Setup Stage The DIR bit in the UEPSTAX register should be at 0. Receiving Setup packets is the same as receiving Bulk Out packets, except that the RXSETUP bit in the UEPSTAX register is set by the USB controller instead of the RXOUTB0 bit to indicate that an Out packet with a Setup PID has been received on the Control endpoint. When the RXSETUP bit has been set, all the other bits of the UEPSTAX register are cleared and an interrupt is triggered if enabled.
AT8xC51SND2C/MP3B The STLCRC bit in the UEPSTAX register is set by the USB controller if the packet stored in FIFO has a corrupted CRC. This bit is updated after each new packet receipt. When all the endpoint FIFO Bytes have been read, the firmware should clear the RXOUTB0 bit to allow the USB controller to store the next OUT packet data into the endpoint FIFO. Until the RXOUTB0 bit has been cleared by the firmware, the data sent by the Host at each OUT transaction will be lost.
When the IN packet has been sent, the TXCMPL bit in the UEPSTAX register is set by the USB controller. This triggers a USB interrupt if enabled. The firmware should clear the TXCMPL bit before filling the endpoint FIFO with new data. The firmware should never write more Bytes than supported by the endpoint FIFO 16.8.4 Isochronous IN Transactions in Ping-pong Mode An endpoint should be first enabled and configured before being able to send Isochronous packets.
AT8xC51SND2C/MP3B 16.9.3 Start of Frame Detection The SOFINT bit in the USBINT register is set when the USB controller detects a Start Of Frame PID. This triggers an interrupt if enabled. The firmware should clear the SOFINT bit to allow the next Start of Frame detection. 16.9.4 Frame Number When receiving a Start Of Frame, the frame number is automatically stored in the UFNUML and UFNUMH registers.
The USB controller is then re-activated. Figure 16-13. Example of a Suspend/Resume Management USB Controller Init SPINT Detection of a SUSPEND State Clear SPINT Set SUSPCLK Disable PLL microcontroller in Power-down WUPCPU Detection of a RESUME State Enable PLL Clear SUSPCLK Clear WUPCPU Bit 16.10.3 Upstream Resume A USB device can be allowed by the Host to send an upstream resume for Remote Wake-up purpose.
AT8xC51SND2C/MP3B Figure 16-14. Example of REMOTE WAKEUP Management USB Controller Init SET_FEATURE: DEVICE_REMOTE_WAKEUP Set RMWUPE SPINT Detection of a SUSPEND state Suspend Management need USB resume enable clocks Clear SPINT UPRSM = 1 Set SDMWUP UPRSM upstream RESUME sent Clear SDRMWUP 16.11 USB Interrupt System 16.11.1 Interrupt System Priorities Figure 16-15. USB Interrupt Control System D+ D- 00 01 10 11 USB Controller EUSB EA IE1.6 IE0.
Table 16-2. 16.11.2 Priority Levels IPHUSB IPLUSB USB Priority Level 0 0 0..................Lowest 0 1 1 1 0 2 1 1 3..................Highest USB Interrupt Control System As shown in Figure 16-16, many events can produce a USB interrupt: 120 • TXCMPL: Transmitted In Data (Table 1 on page 126). This bit is set by hardware when the Host accept a In packet. • RXOUTB0: Received Out Data Bank 0 (Table 1 on page 126).
AT8xC51SND2C/MP3B Figure 16-16. USB Interrupt Control Block Diagram Endpoint X (X = 0..2) TXCMP UEPSTAX.0 RXOUTB0 UEPSTAX.1 RXOUTB1 EPXINT UEPSTAX.6 UEPINT.X RXSETUP EPXIE UEPSTAX.2 UEPIEN.X STLCRC UEPSTAX.3 NAKOUT UEPCONX.5 NAKIN UEPCONX.4 NAKIEN UEPCONX.6 WUPCPU EUSB USBINT.5 EWUPCPU IE1.6 USBIEN.5 EORINT USBINT.4 EEORINT USBIEN.4 SOFINT USBINT.3 ESOFINT USBIEN.3 SPINT USBINT.0 ESPINT USBIEN.
16.12 Registers Table 16-3. USBCON Register USBCON (S:BCh) – USB Global Control Register 7 6 5 4 3 2 1 0 USBE SUSPCLK SDRMWUP - UPRSM RMWUPE CONFG FADDEN Bit Number Bit Mnemonic Description 7 USBE 6 SUSPCLK 5 SDRMWUP 4 - 3 UPRSM 2 RMWUPE USB Enable Bit Set this bit to enable the USB controller. Clear this bit to disable and reset the USB controller, to disable the USB transceiver an to disable the USB controllor clock inputs.
AT8xC51SND2C/MP3B Table 16-4. USBADDR Register USBADDR (S:C6h) – USB Address Register 7 6 5 4 3 2 1 0 FEN UADD6 UADD5 UADD4 UADD3 UADD2 UADD1 UADD0 Bit Number Bit Mnemonic Description 7 6-0 FEN UADD6:0 Function Enable Bit Set to enable the function. The device firmware should set this bit after it has received a USB reset and participate in the following configuration process with the default address (FEN is reset to 0).
Table 16-6. USBIEN Register USBIEN (S:BEh) – USB Global Interrupt Enable Register 7 6 5 4 3 2 1 0 - - EWUPCPU EEORINT ESOFINT - - ESPINT Bit Number Bit Mnemonic Description 7-6 - 5 EWUPCPU 4 EEOFINT End Of Reset Interrupt Enable Bit Set to enable the End Of Reset interrupt. This bit is set after reset. Clear to disable End Of Reset interrupt. 3 ESOFINT Start Of Frame Interrupt Enable Bit Set to enable the SOF interrupt. Clear to disable the SOF interrupt.
AT8xC51SND2C/MP3B Table 16-8. UEPCONX Register UEPCONX (S:D4h) – USB Endpoint X Control Register (X = EPNUM set in UEPNUM) 7 6 5 4 3 2 1 0 EPEN NAKIEN NAKOUT NAKIN DTGL EPDIR EPTYPE1 EPTYPE0 Bit Number Bit Mnemonic Description Endpoint Enable Bit Set to enable the endpoint according to the device configuration. Endpoint 0 should always be enabled after a hardware or USB bus reset and participate in the device configuration.
Table 1. UEPSTAX Register UEPSTAX (S:CEh) – USB Endpoint X Status and Control Register (X = EPNUM set in UEPNUM) 7 6 5 4 3 2 1 0 DIR RXOUTB1 STALLRQ TXRDY STLCRC RXSETUP RXOUTB0 TXCMP Bit Number Bit Mnemonic 7 Description Control Endpoint Direction Bit This bit is relevant only if the endpoint is configured in Control type. Set for the data stage. Clear otherwise. DIR Note: This bit should be configured on RXSETUP interrupt before any other bit is changed.
AT8xC51SND2C/MP3B Table 16-9. UEPRST Register UEPRST (S:D5h) – USB Endpoint FIFO Reset Register 7 6 5 4 3 2 1 0 - - - - - EP2RST EP1RST EP0RST Bit Number Bit Mnemonic Description 7-3 - 2 EP2RST Endpoint 2 FIFO Reset Set and clear to reset the endpoint 2 FIFO prior to any other operation, upon hardware reset or when an USB bus reset has been received.
Table 16-11. UEPINT Register UEPINT (S:F8h Read-only) – USB Endpoint Interrupt Register 7 6 5 4 3 2 1 0 - - - - - EP2INT EP1INT EP0INT Bit Number Bit Mnemonic Description 7-3 - 2 EP2INT Reserved The value read from these bits is always 0. Do not set these bits. Endpoint 2 Interrupt Flag This bit is set by hardware when an endpoint interrupt source has been detected on the endpoint 2.
AT8xC51SND2C/MP3B Table 16-13. UBYCTX Register UBYCTX (S:E2h) – USB Endpoint X Byte Count Register (X = EPNUM set in UEPNUM) 7 6 5 4 3 2 1 0 - BYCT6 BYCT5 BYCT4 BYCT3 BYCT2 BYCT1 BYCT0 Bit Number Bit Mnemonic Description 7 - 6-0 BYCT7:0 Reserved The value read from this bits is always 0. Do not set this bit. Byte Count Byte count of a received data packet. This Byte count is equal to the number of data Bytes received after the Data PID. Reset Value = 0000 0000b Table 16-14.
Table 16-15. UFNUMH Register UFNUMH (S:BBh, Read-only) – USB Frame Number High Register 7 6 5 4 3 2 1 0 - - CRCOK CRCERR - FNUM10 FNUM9 FNUM8 Bit Number Bit Mnemonic Description 7-3 - 5 CRCOK Reserved The value read from these bits is always 0. Do not set these bits. Frame Number CRC OK Bit Set by hardware after a non corrupted Frame Number in Start of Frame Packet is received. Updated after every Start Of Frame packet reception.
AT8xC51SND2C/MP3B 17. IDE/ATAPI Interface The AT8xC51SND2C provides an IDE/ATAPI interface allowing connection of devices such as CD-ROM reader, CompactFlash cards, Hard Disk Drive, etc. It consists of a 16-bit data transfer (read or write) between the AT8xC51SND2C and the IDE device. 17.1 Description The IDE interface mode is enabled by setting the EXT16 bit in AUXR (see Figure 7-5, page 29).
Figure 17-2. IDE Write Waveforms CPU Clock ALE WR(1) P0 P2 Notes: 17.1.1 P2 DPL or Ri D7:0 DPH or P2(2),(3) D15:8 P2 1. WR signal may be stretched using M0 bit in AUXR register. 2. When executing MOVX @Ri instruction, P2 outputs SFR content. 3. When executing MOVX @DPTR instruction, if DPHDIS is set (Page Access Mode), P2 outputs SFR content instead of DPH. IDE Device Connection Figure 17-3 and Figure 17-4 show 2 examples on how to interface up to 2 IDE devices to the AT8xC51SND2C.
AT8xC51SND2C/MP3B Table 17-1. 17.2 External Data Memory Interface Signals Signal Name Type Alternate Function A15:8 I/O Address Lines Upper address lines for the external bus. Multiplexed higher address and data lines for the IDE interface. P2.7:0 AD7:0 I/O Address/Data Lines Multiplexed lower address and data lines for the IDE interface. P0.7:0 ALE O Address Latch Enable ALE signals indicates that valid address information is available on lines AD7:0.
18. MultiMedia Card Controller The AT8xC51SND2C implements a MultiMedia Card (MMC) controller. The MMC is used to store MP3 encoded audio files in removable Flash memory cards that can be easily plugged or removed from the application. 18.1 Card Concept The basic MultiMedia Card concept is based on transferring data via a minimum number of signals. 18.1.1 Card Signals The communication signals are: 18.1.2 • CLK: with each cycle of this signal a one bit transfer on the command and data lines is done.
AT8xC51SND2C/MP3B The bus communication uses a special protocol (MultiMedia Card bus protocol) which is applicable for all devices. Therefore, the payload data transfer between the host and the cards can be bi-directional. 18.2.1 Bus Lines The MultiMedia Card bus architecture requires all cards to be connected to the same set of lines. No card has an individual connection to the host or other devices, which reduces the connection costs of the MultiMedia Card system.
Figure 18-1. Sequential Read Operation Stop Command MCMD Command Response Command MDAT Response Data Stream Data Transfer Operation Data Stop Operation Figure 18-2.
AT8xC51SND2C/MP3B 18.2.3 Command Token Format As shown in Figure 18-6, commands have a fixed code length of 48 bits. Each command token is preceded by a Start bit: a low level on MCMD line and succeeded by an End bit: a high level on MCMD line. The command content is preceded by a Transmission bit: a high level on MCMD line for a command token (host to card) and succeeded by a 7 - bit CRC so that transmission errors can be detected and the operation may be repeated.
Table 18-2. Bit Position 47 46 45:40 39:8 7:1 0 Width (bits) 1 1 6 32 7 1 Value ‘0’ ‘0’ - - - ‘1’ Start bit Transmission bit Command Index Card Status CRC7 End bit Description Table 18-3. R2 Response Format (CID and CSD registers) Bit Position 135 134 [133:128] [127:1] 0 Width (bits) 1 1 6 32 1 Value ‘0’ ‘0’ ‘111111’ - ‘1’ Description Start bit Transmission bit Reserved Argument End bit Table 18-4.
AT8xC51SND2C/MP3B Figure 18-8. Data Token Format Sequential Data 0 Block Data 0 Content Content 1 CRC 1 Block Length 18.2.6 Clock Control The MMC bus clock signal can be used by the host to turn the cards into energy saving mode or to control the data flow (to avoid under-run or over-run conditions) on the bus. The host is allowed to lower the clock frequency or shut it down. There are a few restrictions the host must follow: 18.
Figure 18-9. MMC Controller Block Diagram MCLK Clock Generator OSC CLOCK Command Line Controller MCMD MMC Interrupt Request Interrupt Controller Data Line Controller Internal Bus 18.4 MDAT 8 Clock Generator The MMC clock is generated by division of the oscillator clock (FOSC) issued from the Clock Controller block as detailed in Section "Oscillator", page 13. The division factor is given by MMCD7:0 bits in MMCLK register, a value of 0x00 stops the MMC clock.
AT8xC51SND2C/MP3B Figure 18-12. Command Line Controller Block Diagram TX Pointer 5-Byte FIFO CTPTR MMCMD Write MMCON0.4 Data Converter // -> Serial CRC7 Generator TX COMMAND Line Finished State Machine CFLCK MMSTA.0 Command Transmitter RX Pointer 17 - Byte FIFO EOCI CMDEN MCMD MMCON1.0 Data Converter Serial -> // MMSTA.2 MMSTA.1 CRC7S RESPFS CRC7 and Format Checker MMCMD Read CRPTR MMCON0.5 RX COMMAND Line Finished State Machine RESPEN Command Receiver 18.5.1 MMINT.5 RFMT MMINT.
Figure 18-13. Command Transmission Flow Command Transmission Configure Response RESPEN = X RFMT = X CRCDIS = X Load Command in Buffer MMCMD = index MMCMD = argument Transmit Command CMDEN = 1 CMDEN = 0 18.5.2 Command Receiver The end of the response reception is signalled to you by the EORI flag in MMINT register. This flag may generate an MMC interrupt request as detailed in Section "Interrupt", page 148.
AT8xC51SND2C/MP3B Figure 18-14. Data Line Controller Block Diagram MMINT.0 MMINT.2 MMSTA.3 MMSTA.4 F1EI F1FI DATFS CRC16S CRC16 and Format Checker Data Converter Serial -> // 8-Byte TX Pointer FIFO 1 DTPTR MMCON0.6 RX Pointer DRPTR MMCON0.7 18.6.1 MCBI CBUSY MMINT.1 MMSTA.5 16-Byte FIFO MMDAT MDAT Data Converter // -> Serial CRC16 Generator 8-Byte MMINT.4 DATA Line Finished State Machine FIFO 2 F2EI F2FI MMINT.1 MMINT.3 DFMT MBLOCK DATEN MMCON0.2 MMCON0.3 MMCON1.
Figure 18-15. Data Controller Configuration Flows 18.6.3 18.6.3.1 Data Stream Configuration Data Single Block Configuration Data Multi-Block Configuration Configure Format DFMT = 0 Configure Format DFMT = 1 MBLOCK = 0 BLEN3:0 = XXXXb Configure Format DFMT = 1 MBLOCK = 1 BLEN3:0 = XXXXb Data Transmitter Configuration For transmitting data to the card user must first configure the data controller in transmission mode by setting the DATDIR bit in MMCON1 register.
AT8xC51SND2C/MP3B which is set every time CBUSY toggles, i.e. when the card enters and exits its busy state. This flag may generate an MMC interrupt request as detailed in Section "Interrupt", page 148. Figure 18-16.
Figure 18-17.
AT8xC51SND2C/MP3B may reset the data controller and its internal state machine by setting and clearing the DCR bit in MMCON2 register. This time-out may be disarmed after receiving 8 data (F1FI flag set) or after receiving end of frame (EOFI flag set) in case of block length less than 8 data (1, 2 or 4). 18.6.4.3 Data Reading Data is read from the FIFO by reading to MMDAT register. Each time one FIFO becomes full (F1FI or F2FI set), user is requested to flush this FIFO by reading 8 data. Figure 18-18.
Figure 18-19. Data Block Reception Flows Data Block Reception Data Block Initialization Data Block Reception ISR Start Transmission DATEN = 1 DATEN = 0 Unmask FIFOs Full F1FM = 0 F2FM = 0 FIFO Full? F1EI or F2EI = 1? FIFO Full? F1EI or F2EI = 1? Start Transmission DATEN = 1 DATEN = 0 FIFO Reading read 8 data from MMDAT No More Data To Receive? FIFO Reading read 8 data from MMDAT No More Data To Receive? a. Polling mode 18.6.5 Mask FIFOs Full F1FM = 1 F2FM = 1 b.
AT8xC51SND2C/MP3B The interrupt request is generated each time an unmasked flag is set, and the global MMC controller interrupt enable bit is set (EMMC in IEN1 register). Reading the MMINT register automatically clears the interrupt flags (acknowledgment). This implies that register content must be saved and tested interrupt flag by interrupt flag to be sure not to forget any interrupts. Figure 18-20. MMC Controller Interrupt System MCBI MMINT.7 MCBM MMMSK.7 EORI MMINT.6 EORM EOCI MMMSK.6 MMINT.
18.8 Registers Table 18-8. MMCON0 Register MMCON0 (S:E4h) – MMC Control Register 0 7 6 5 4 3 2 1 0 DRPTR DTPTR CRPTR CTPTR MBLOCK DFMT RFMT CRCDIS Bit Number Bit Mnemonic Description 7 DRPTR Data Receive Pointer Reset Bit Set to reset the read pointer of the data FIFO. Clear to release the read pointer of the data FIFO. 6 DTPTR Data Transmit Pointer Reset Bit Set to reset the write pointer of the data FIFO. Clear to release the write pointer of the data FIFO.
AT8xC51SND2C/MP3B Table 18-9. MMCON1 Register MMCON1 (S:E5h) – MMC Control Register 1 7 6 5 4 3 2 1 0 BLEN3 BLEN2 BLEN1 BLEN0 DATDIR DATEN RESPEN CMDEN Bit Number Bit Mnemonic Description 7-4 BLEN3:0 Block Length Bits Refer to Table 18-7 for bits description. Do not program value > 1011b 3 DATDIR Data Direction Bit Set to select data transfer from host to card (write mode). Clear to select data transfer from card to host (read mode).
Table 18-11. MMSTA Register MMSTA (S:DEh Read Only) – MMC Control and Status Register 7 6 5 4 3 2 1 0 - - CBUSY CRC16S DATFS CRC7S RESPFS CFLCK Bit Number Bit Mnemonic Description 7-6 - 5 CBUSY Card Busy Flag Set by hardware when the card sends a busy state on the data line. Cleared by hardware when the card no more sends a busy state on the data line. CRC16S CRC16 Status Bit Transmission mode Set by hardware when the token response reports a good CRC.
AT8xC51SND2C/MP3B Table 18-12. MMINT Register MMINT (S:E7h Read Only) – MMC Interrupt Register 7 6 5 4 3 2 1 0 MCBI EORI EOCI EOFI F2FI F1FI F2EI F1EI Bit Number Bit Mnemonic Description 7 MCBI MMC Card Busy Interrupt Flag Set by hardware when the card enters or exits its busy state (when the busy signal is asserted or deasserted on the data line). Cleared when reading MMINT. 6 EORI End of Response Interrupt Flag Set by hardware at the end of response reception.
Table 18-13. MMMSK Register MMMSK (S:DFh) – MMC Interrupt Mask Register 7 6 5 4 3 2 1 0 MCBM EORM EOCM EOFM F2FM F1FM F2EM F1EM Bit Number Bit Mnemonic Description 7 MCBM MMC Card Busy Interrupt Mask Bit Set to prevent MCBI flag from generating an MMC interrupt. Clear to allow MCBI flag to generate an MMC interrupt. 6 EORM End Of Response Interrupt Mask Bit Set to prevent EORI flag from generating an MMC interrupt. Clear to allow EORI flag to generate an MMC interrupt.
AT8xC51SND2C/MP3B Table 18-15. MMDAT Register MMDAT (S:DCh) – MMC Data Register 7 6 5 4 3 2 1 0 MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0 Bit Number Bit Mnemonic Description 7-0 MD7:0 MMC Data Byte Input (write) or output (read) register of the data FIFO. Reset Value = 1111 1111b Table 18-16.
19. Synchronous Peripheral Interface The AT8xC51SND2C implements a Synchronous Peripheral Interface with master and slave modes capability. Figure 19-1 shows an SPI bus configuration using the AT8xC51SND2C as master connected to slave peripherals while Figure 19-2 shows an SPI bus configuration using the AT8xC51SND2C as slave of an other master.
AT8xC51SND2C/MP3B 19.1 Description The SPI controller interfaces with the C51 core through three special function registers: SPCON, the SPI control register (see Table 19-2); SPSTA, the SPI status register (see Table 19-3); and SPDAT, the SPI data register (see Table 19-4). 19.1.1 Master Mode The SPI operates in master mode when the MSTR bit in SPCON is set. Figure 19-3 shows the SPI block diagram in master mode. Only a master SPI module can initiate transmissions.
When the AT8xC51SND2C is the only slave on the bus, it can be useful not to use SS# pin and get it back to I/O functionality. This is achieved by setting SSDIS bit in SPCON. This bit has no effect when CPHA is cleared (see Section "SS Management", page 159). Figure 19-4. SPI Slave Mode Block Diagram MISO/P4.2 I 8-bit Shift Register SPDAT WR SPDAT RD SCK/P4.2 Q Internal Bus MOSI/P4.1 Control and Clock Logic SS/P4.3 SPIF SPSTA.7 SSDIS SPCON.5 Note: 19.1.3 CPHA CPOL SPCON.2 SPCON.3 1.
AT8xC51SND2C/MP3B For simplicity, Figure 19-5 and Figure 19-6 depict the SPI waveforms in idealized form and do not provide precise timing information. For timing parameters refer to the Section “AC Characteristics”. Note: 1. When the peripheral is disabled (SPEN = 0), default SCK line is high level. Figure 19-5.
Figure 19-7. SS Timing Diagram SI/SO Byte 1 Byte 2 Byte 3 SS (CPHA = 0) SS (CPHA = 1) 19.1.6 Error Conditions The following flags signal the SPI error conditions: 19.2 • MODF in SPSTA signals a mode fault. MODF flag is relevant only in master mode when SS usage is enabled (SSDIS bit cleared). It signals when set that an other master on the bus has asserted SS pin and so, may create a conflict on the bus with 2 master sending data at the same time.
AT8xC51SND2C/MP3B 19.3.2 Slave Configuration The SPI operates in slave mode when the MSTR bit in SPCON is cleared and data has been loaded is SPDAT. 19.3.3 Data Exchange There are 2 possible methods to exchange data in master and slave modes: 19.3.4 • polling • interrupts Master Mode with Polling Policy Figure 19-9 shows the initialization phase and the transfer phase flows using the polling method. Using this flow prevents any overrun error occurrence.
Figure 19-9. Master SPI Polling Flows SPI Initialization Polling Policy SPI Transfer Polling Policy Disable interrupt SPIE = 0 Select Slave Pn.x = L Select Master Mode MSTR = 1 Start Transfer write data in SPDAT Select Bit Rate program SPR2:0 End Of Transfer? SPIF = 1? Select Format program CPOL & CPHA Get Data Received read SPDAT Enable SPI SPEN = 1 Last Transfer? Deselect Slave Pn.x = H 19.3.
AT8xC51SND2C/MP3B Figure 19-10. Master SPI Interrupt Flows SPI Initialization Interrupt Policy SPI Interrupt Service Routine Select Master Mode MSTR = 1 Read Status Read SPSTA Select Bit Rate program SPR2:0 Get Data Received read SPDAT Select Format program CPOL & CPHA Start New Transfer write data in SPDAT Enable interrupt ESPI =1 Last Transfer? Enable SPI SPEN = 1 Deselect Slave Pn.x = H Select Slave Pn.x = L Disable interrupt SPIE = 0 Start Transfer write data in SPDAT 19.3.
Figure 19-11. Slave SPI Polling Flows SPI Initialization Polling Policy Disable interrupt SPIE = 0 SPI Transfer Polling Policy Data Received? SPIF = 1? Select Slave Mode MSTR = 0 Get Data Received read SPDAT Select Format program CPOL & CPHA Prepare Next Transfer write data in SPDAT Enable SPI SPEN = 1 Prepare Transfer write data in SPDAT 19.3.7 Slave Mode with Interrupt Policy Figure 19-10 shows the initialization phase and the transfer phase flows using the interrupt.
AT8xC51SND2C/MP3B Figure 19-12.
19.4 Registers Table 19-2. SPCON Register SPCON (S:C3h) – SPI Control Register 7 6 5 4 3 2 1 0 SPR2 SPEN SSDIS MSTR CPOL CPHA SPR1 SPR0 Bit Number Bit Mnemonic Description 7 SPR2 SPI Rate Bit 2 Refer to Table 19-1 for bit rate description. 6 SPEN SPI Enable Bit Set to enable the SPI interface. Clear to disable the SPI interface. 5 SSDIS Slave Select Input Disable Bit Set to disable SS in both master and slave modes. In slave mode this bit has no effect if CPHA = 0.
AT8xC51SND2C/MP3B Table 19-3. SPSTA Register SPSTA (S:C4h) – SPI Status Register 7 6 5 4 3 2 1 0 SPIF WCOL - MODF - - - - Bit Number Bit Mnemonic Description 7 SPIF 6 WCOL 5 - 4 MODF 3-0 - SPI Interrupt Flag Set by hardware when an 8-bit shift is completed. Cleared by hardware when reading or writing SPDAT after reading SPSTA. Write Collision Flag Set by hardware to indicate that a collision has been detected.
20. Serial I/O Port The serial I/O port in the AT8xC51SND2C provides both synchronous and asynchronous communication modes. It operates as a Synchronous Receiver and Transmitter in one single mode (Mode 0) and operates as an Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2 and 3). Asynchronous modes support framing error detection and multiprocessor communication with automatic address recognition. 20.
AT8xC51SND2C/MP3B Figure 20-1. Timer 1 Baud Rate Generator Block Diagram PER CLOCK ÷6 0 TL1 (8 bits) 1 Overflow ÷2 T1 0 1 To serial Port C/T1# TMOD.6 SMOD1 INT1 PCON.7 TH1 (8 bits) GATE1 T1 CLOCK TMOD.7 TR1 TCON.6 20.2.2 Internal Baud Rate Generator When using the Internal Baud Rate Generator, the Baud Rate is derived from the overflow of the timer.
Figure 20-3. Serial I/O Port Block Diagram (Mode 0) SCON.6 SCON.7 SM1 SM0 SBUF Tx SR Mode Decoder RXD M3 M2 M1 M0 SBUF Rx SR Mode Controller PER CLOCK 20.3.1 TI RI SCON.1 SCON.0 Baud Rate Controller BRG CLOCK TXD Transmission (Mode 0) To start a transmission mode 0, write to SCON register clearing bits SM0, SM1. As shown in Figure 20-4, writing the Byte to transmit to SBUF register starts the transmission.
AT8xC51SND2C/MP3B 20.3.3 Baud Rate Selection (Mode 0) In mode 0, the baud rate can be either, fixed or variable. As shown in Figure 20-6, the selection is done using M0SRC bit in BDRCON register. Figure 20-7 gives the baud rate calculation formulas for each baud rate source. Figure 20-6. Baud Rate Source Selection (mode 0) PER CLOCK ÷6 0 To Serial Port 1 IBRG0 CLOCK M0SRC BDRCON.0 Figure 20-7. Baud Rate Formulas (Mode 0) Baud_Rate= Baud_Rate= FPER 6 BRL= 256 - a. Fixed Formula 20.
Figure 20-9. Data Frame Format (Mode 1) Mode 1 D0 D1 D2 Start bit 20.4.0.2 D3 D4 D5 D6 D7 8-bit data Stop bit Modes 2 and 3 Modes 2 and 3 are full-duplex, asynchronous modes. The data frame (see Figure 20-10) consists of 11 bits: one start bit, eight data bits (transmitted and received LSB first), one programmable ninth data bit and one stop bit. Serial data is transmitted on the TXD pin and received on the RXD pin. On receive, the ninth bit is read from RB8 bit in SCON register.
AT8xC51SND2C/MP3B 20.4.4 Baud Rate Selection (Modes 1 and 3) In modes 1 and 3, the Baud Rate is derived either from the Timer 1 or the Internal Baud Rate Generator and allows different baud rate in reception and transmission. As shown in Figure 20-12 the selection is done using RBCK and TBCK bits in BDRCON register.
Table 20-2. Internal Baud Rate Generator Value FPER = 6 MHz(1) FPER = 8 MHz(1) Baud Rate SPD SMOD 1 BRL Error % SPD SMOD 1 BRL Error % SPD SMOD 1 BRL Error % 115200 - - - - - - - - - - - - 57600 - - - - 1 1 247 3.55 1 1 245 1.36 38400 1 1 246 2.34 1 1 243 0.16 1 1 240 1.73 19200 1 1 236 2.34 1 1 230 0.16 1 1 223 1.36 9600 1 1 217 0.16 1 1 204 0.16 1 1 191 0.16 4800 1 1 178 0.16 1 1 152 0.16 1 1 126 0.
AT8xC51SND2C/MP3B Figure 20-15. Baud Rate Formula (Mode 2) Baud_Rate= 20.5 2SMOD1 ⋅ FPER 32 Multiprocessor Communication (Modes 2 and 3) Modes 2 and 3 provide a ninth-bit mode to facilitate multiprocessor communication. To enable this feature, set SM2 bit in SCON register. When the multiprocessor communication feature is enabled, the serial Port can differentiate between data frames (ninth bit clear) and address frames (ninth bit set).
SADEN = 1111 1010b Given = 1111 0X0Xb Slave B:SADDR = 1111 0011b SADEN = 1111 1001b Given = 1111 0XX1b Slave C:SADDR = 1111 0011b SADEN = 1111 1101b Given = 1111 00X1b The SADEN Byte is selected so that each slave may be addressed separately. For slave A, bit 0 (the LSB) is a don’t-care bit; for slaves B and C, bit 0 is a 1. To communicate with slave A only, the master must send an address where bit 0 is clear (e.g. 1111 0000B). For slave A, bit 1 is a 0; for slaves B and C, bit 1 is a don’t care bit.
AT8xC51SND2C/MP3B 20.7 Interrupt The Serial I/O Port handles 2 interrupt sources that are the “end of reception” (RI in SCON) and “end of transmission” (TI in SCON) flags. As shown in Figure 20-16 these flags are combined together to appear as a single interrupt source for the C51 core. Flags must be cleared by software when executing the serial interrupt service routine. The serial interrupt is enabled by setting ES bit in IEN0 register.
20.8 Registers Table 20-3. SCON Register SCON (S:98h) – Serial Control Register 7 6 5 4 3 2 1 0 FE/SM0 OVR/SM1 SM2 REN TB8 RB8 TI RI Bit Number Bit Mnemonic Description FE 7 Framing Error Bit To select this function, set SMOD0 bit in PCON register. Set by hardware to indicate an invalid stop bit. Must be cleared by software. SM0 Serial Port Mode Bit 0 Refer to Table 20-1 for mode selection. SM1 Serial Port Mode Bit 1 Refer to Table 20-1 for mode selection.
AT8xC51SND2C/MP3B Table 20-4. SBUF Register SBUF (S:99h) – Serial Buffer Register 7 6 5 4 3 2 1 0 SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 Bit Number Bit Mnemonic Description 7-0 SD7:0 Serial Data Byte Read the last data received by the serial I/O Port. Write the data to be transmitted by the serial I/O Port. Reset value = XXXX XXXXb Table 20-5.
Table 20-7. BDRCON Register BDRCON (S:92h) – Baud Rate Generator Control Register 7 6 5 4 3 2 1 0 - - - BRR TBCK RBCK SPD M0SRC Bit Number Bit Mnemonic Description 7-5 - 4 BRR Baud Rate Run Bit Set to enable the baud rate generator. Clear to disable the baud rate generator. 3 TBCK Transmission Baud Rate Selection Bit Set to select the baud rate generator as transmission baud rate generator. Clear to select the Timer 1 as transmission baud rate generator.
AT8xC51SND2C/MP3B 21. Two-wire Interface (TWI) Controller The AT8xC51SND2C implements a TWI controller supporting the four standard master and slave modes with multimaster capability. Thus, it allows connection of slave devices like LCD controller, audio DAC, etc., but also external master controlling where the AT8xC51SND2C is used as a peripheral of a host. The TWI bus is a bi-directional TWI serial communication standard. It is designed primarily for simple but efficient integrated circuit control.
Figure 21-2. Complete Data Transfer on TWI Bus SDA MSB Slave Address SCL 1 R/W ACK direction signal bit from receiver 2 8 Nth data Byte 9 S 1 2 ACK signal from receiver 8 9 Clock Line Held Low While Serial Interrupts Are Serviced P/S The four operating modes are: • Master transmitter • Master receiver • Slave transmitter • Slave receiver Data transfer in each mode of operation are shown in Figure 21-3 through Figure 21-6.
AT8xC51SND2C/MP3B Table 21-1. Serial Clock Rates SSCRx 2 1 0 FPER = 6 MHz FPER = 8 MHz FPER = 10 MHz FPER Divided By 0 0 0 47 62.5 78.125 128 0 0 1 53.5 71.5 89.3 112 0 1 0 62.5 83 104.2(1) 96 (1) 0 1 1 75 100 125 1 0 0 12.5 16.5 20.83 1 0 1 100 1 1 0 200(1) 1 1 Note: 21.1.2 Bit Frequency (kHz) 1 0.5 < ⋅ < 125 133.3 (1) 166.7 266.7(1) (1) 0.67 < ⋅ < 166.7 80 480 (1) 60 333.3(1) (1) 0.81 < ⋅ < 208.
When the slave address and the direction bit have been transmitted and an acknowledgment bit has been received, the serial interrupt flag is set again and a number of status code in SSSTA are possible. There are 40h, 48h or 38h for the master mode and also 68h, 78h or B0h if the slave mode was enabled (SSAA = logic 1). The appropriate action to be taken for each of these status code is detailed in Table 21-6. This scheme is repeated until a STOP condition is transmitted.
AT8xC51SND2C/MP3B If the SSAA bit is reset during a transfer, the controller will transmit the last Byte of the transfer and enter state C0h or C8h. The controller is switched to the not addressed slave mode and will ignore the master receiver if it continues the transfer. Thus the master receiver receives all 1’s as serial data. While SSAA is reset, the controller does not respond to its own slave address.
Figure 21-3.
AT8xC51SND2C/MP3B Figure 21-4.
Figure 21-5. Format and States in the Slave Receiver Mode Reception of the own slave address and one or more data Bytes.
AT8xC51SND2C/MP3B Figure 21-6. Format and States in the Slave Transmitter Mode Reception of the own slave address and transmission of one or more data Bytes. S SLA R A Data A8h Arbitration lost as master and addressed as slave A B8h Data A P or S C0h A B0h Last data Byte transmitted. Switched to not addressed slave (SSAA = 0).
Table 21-2.
AT8xC51SND2C/MP3B Table 21-3. Status for Master Receiver Mode Application Software Response Status Code SSSTA To SSCON Status of the TWI Bus and TWI Hardware To/From SSDAT SSSTA SSSTO SSI SSAA Next Action Taken by TWI Hardware 08h A START condition has Write SLA+R been transmitted X 0 0 X Write SLA+R X 0 0 X 10h A repeated START condition has been transmitted Write SLA+W X 0 0 X SLA+W will be transmitted. Logic will switch to master transmitter mode.
Table 21-4.
AT8xC51SND2C/MP3B Table 21-5.
Table 21-6.
AT8xC51SND2C/MP3B 21.2 Registers Table 21-8. AUXCON Register AUXCON (S:90h) – Auxiliary Control Register 7 6 5 4 3 2 1 0 SDA SCL - AUDCDOUT AUDCDIN AUDCCLK AUDCCS KIN0 Bit Number Bit Mnemonic 7 SDA Description TWI Serial Data SDA is the bidirectional Two Wire data line. 6 SCL Audio DAC Control 5:1 0 TWI Serial Clock When TWI controller is in master mode, SCL outputs the serial clock to the slave peripherals.
Table 21-9. SSCON Register SSCON (S:93h) – Synchronous Serial Control Register 7 6 5 4 3 2 1 0 SSCR2 SSPE SSSTA SSSTO SSI SSAA SSCR1 SSCR0 Bit Number Bit Mnemonic Description 7 SSCR2 6 SSPE Synchronous Serial Peripheral Enable Bit Set to enable the controller. Clear to disable the controller. 5 SSSTA Synchronous Serial Start Flag Set to send a START condition on the bus. Clear not to send a START condition on the bus.
AT8xC51SND2C/MP3B Table 21-10. SSSTA Register SSSTA (S:94h) – Synchronous Serial Status Register 7 6 5 4 3 2 1 0 SSC4 SSC3 SSC2 SSC1 SSC0 0 0 0 Bit Number Bit Mnemonic Description 7:3 SSC4:0 2:0 0 Synchronous Serial Status Code Bits 0 to 4 Refer to Table 21-2 to Table 21-6 for status description. Always 0. Reset Value = F8h Table 21-11.
AT8xC51SND2C/MP3B 4341H–MP3–10/07
AT8xC51SND2C/MP3B 22. Analog to Digital Converter The AT8XSND2CMP3B implement a 2-channel 10-bit (8 true bits) analog to digital converter (ADC). First channel of this ADC can be used for battery monitoring while the second one can be used for voice sampling at 8 kHz. The AT8xC51SND2C does not include the A/D converter. 22.
Figure 22-2. Timing Diagram CLK TADCLK ADEN TSETUP ADSST TCONV ADEOC 22.1.1 Clock Generator The ADC clock is generated by division of the peripheral clock (see details in section “X2 Feature”, page 14). The division factor is then given by ADCP4:0 bits in ADCLK register. Figure 223 shows the ADC clock generator and its calculation formula(1). Figure 22-3.
AT8xC51SND2C/MP3B version (see Section "End Of Conversion", page 201). This bit is cleared by hardware at the end of the conversion. Notes: 22.1.4 1. Only the CPU activity is frozen, peripherals are not affected by the Pseudo-Idle mode. 2. If some interrupts occur during the Pseudo-Idle mode, they will be delayed and processed, according to their priority after the end of the conversion. 3. Concurrently with ADSST bit.
enabled by setting EADC bit in IEN1 register. This flag is set by hardware and must be reset by software. 22.2 Registers Table 3. ADCON Register ADCON (S:F3h) – ADC Control Register 7 6 5 4 3 2 1 0 - ADIDL ADEN ADEOC ADSST - - ADCS Bit Number Bit Mnemonic Description 7 - 6 ADIDL ADC Pseudo-Idle Mode Set to suspend the CPU core activity (pseudo-idle mode) during conversion. Clear by hardware at the end of conversion. 5 ADEN ADC Enable Bit Set to enable the A to D converter.
AT8xC51SND2C/MP3B Table 5. ADDH Register ADDH (S:F5h Read Only) – ADC Data High Byte Register 7 6 5 4 3 2 1 0 ADAT9 ADAT8 ADAT7 ADAT6 ADAT5 ADAT4 ADAT3 ADAT2 Bit Number Bit Mnemonic Description 7-0 ADAT9:2 ADC Data 8 Most Significant Bits of the 10-bit ADC data. Reset Value = 0000 0000b Table 6.
23. Keyboard Interface The AT8xC51SND2C implement a keyboard interface allowing the connection of a keypad. It is based on one input with programmable interrupt capability on both high or low level. This input allows exit from idle and power down modes. 23.1 Description The keyboard interfaces with the C51 core through 2 special function registers: KBCON, the keyboard control register (see Table 23-2); and KBSTA, the keyboard control and status register (see Table 23-3).
AT8xC51SND2C/MP3B 23.2 Registers Table 23-1. AUXCON Register AUXCON (S:90h) – Auxiliary Control Register 7 6 5 4 3 2 1 0 SDA SCL - AUDCDOUT AUDCDIN AUDCCLK AUDCCS KIN0 Bit Number Bit Mnemonic Description TWI Lines 7:6 Refer to TWI section. Audio DAC Control 5:1 0 Refer to Audio DAC section. KIN0 Keyboard Input Interrupt. Reset Value = 1111 1111b Table 23-2.
Table 23-3. KBSTA Register KBSTA (S:A4h) – Keyboard Control and Status Register 7 6 5 4 3 2 1 0 KPDE - - - - - - KINF0 Bit Number Bit Mnemonic Description 7 KPDE 6-1 - 0 KINF0 Keyboard Power Down Enable Bit Set to enable exit of power down mode by the keyboard interrupt. Clear to disable exit of power down mode by the keyboard interrupt. Reserved The value read from these bits is always 0. Do not set these bits.
AT8xC51SND2C/MP3B 24. Electrical Characteristics 24.1 Absolute Maximum Rating Storage Temperature ......................................... -65 to +150°C Voltage on any other Pin to VSS .................................... -0.3 *NOTICE: to +4.0 V IOL per I/O Pin ................................................................. 5 mA Power Dissipation ............................................................. 1 W Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage.
Table 24-1. Symbol Digital DC Characteristics VDD = 2.7 to 3.3 V, TA = -40 to +85°C Parameter Min AT89C51SND2C Operating Current Typ(1) Max (3) X1 / X2 mode 7/ 11.5 9/ 14.5 10.5 / 18 Units VDD < 3.3 V mA IDD X1 / X2 mode 7/ 11.5 9/ 14.5 10.5 / 18 AT83SND2C Operating Current AT89C51SND2C (3) Idle Mode Current X1 / X2 mode 6.3 / 9.1 7.4 / 11.3 8.5 / 14 Test Conditions 12 MHz 16 MHz 20 MHz VDD < 3.3 V mA 12 MHz 16 MHz 20 MHz VDD < 3.
AT8xC51SND2C/MP3B 24.2.1.1 IDD, IDL and IPD Test Conditions Figure 24-1. IDD Test Condition, Active Mode VDD VDD RST (NC) Clock Signal VDD PVDD UVDD AUDVDD X2 X1 IDD VDD P0 VSS PVSS UVSS AUDVSS VSS TST All other pins are unconnected Figure 24-2. IDL Test Condition, Idle Mode VDD RST VSS (NC) Clock Signal VDD PVDD UVDD AUDVDD X2 X1 IDL VDD P0 VSS PVSS UVSS AUDVSS VSS TST All other pins are unconnected Figure 24-3.
24.2.2 24.2.2.1 Oscillator & Crystal Schematic Figure 24-4. Crystal Connection X1 C1 Q C2 VSS Note: 24.2.2.2 X2 For operation with most standard crystals, no external components are needed on X1 and X2. It may be necessary to add external capacitors on X1 and X2 to ground in special cases (max 10 pF). X1 and X2 may not be used to drive other circuits. Parameters Table 24-3. Oscillator & Crystal Characteristics VDD = 2.7 to 3.3 V, TA = -40 to +85°C Symbol 24.2.3.
AT8xC51SND2C/MP3B VDD = 2.7 to 3.3 V, TA = -40 to +85°C Symbol 24.2.4 24.2.4.1 Parameter Min Typ Max Unit R Filter Resistor 100 Ω C1 Filter Capacitance 1 10 nF C2 Filter Capacitance 2 2.2 nF USB Connection Schematic Figure 24-6. USB Connection VDD VBUS To Power Supply D+ RFS D+ RUSB D- D- RUSB GND VSS 24.2.4.2 Parameters Table 24-5. USB Termination Characteristics VDD = 3 to 3.
Symbol VOS Parameter Conditions Min Typ Max Unit Output differential offset full gain -20 0 20 mV Input impedance Active state 12K 20k 30k W ZLFP Output load Full Power mode 6 8 32 W ZLLP Output load Low-Power mode 100 150 300 W - - 100 pF - 60 - dB 50 - 20000 Hz - - 10 ms ZIN CL PSRR BW tUP Capacitive load Power supply rejection ratio Output Frequency bandwidth Output setup time 200 – 2kHz Differential output 1KHz reference frequency 3dB attenuation.
AT8xC51SND2C/MP3B Figure 24-9. Dissipated Power vs Output Power, AUDVBAT = 3.2V 600 550 Dissipated Power [mW] 500 450 400 350 8 Ohms load 300 6.5 Ohms load 250 200 150 100 50 0 0 100 200 300 400 500 600 700 800 Output Power [mW] 24.2.6.2 DAC AUDVDD, HSVDD = 2.8 V, Ta=25°C, typical case, unless otherwise noted All noise and distortion specifications are measured in the 20 Hz to 0.425xFs and A-weighted filtered. Full Scale levels scale proportionally with the analog supply voltage.
Table 24-6.
AT8xC51SND2C/MP3B Table 24-6. Audio DAC Specification (Continued) OVERALL MIN Left-channel to right-channel crosstalk (@ 1kHz) TYP MAX UNITS -90 -80 dB ANALOG PERFORMANCE – Differential mono input amplifier Differential input level for full scale output - 0dBFS Level @ AUDVDD, HSVDD = 2.8 V and 0 dB gain Input common mode voltage 1.65 Vppdif 583 mVrms 0.
24.2.7 Digital Filters Transfer Function Figure 24-10. Channel Filter Figure 24-11.
AT8xC51SND2C/MP3B 24.2.7.1 Audio DAC and PA Connection Figure 24-12. DAC and PA Connection PAINN Battery AUDVSS 3.2V to 5.
Table 24-7. DAC and PA Characteristics Symbol 24.2.8 24.2.8.
AT8xC51SND2C/MP3B 24.3 AC Characteristics 24.3.1 24.3.1.1 External Program Bus Cycles Definition of Symbols Table 24-9. External Program Bus Cycles Timing Symbol Definitions Signals 24.3.1.2 Conditions A Address H High I Instruction In L Low L ALE V Valid P PSEN X No Longer Valid Z Floating Timings Test conditions: capacitive load on all pins= 50 pF. Table 24-10. External Program Bus Cycle - Read AC Timings VDD = 2.7 to 3.
24.3.1.3 Waveforms Figure 24-14. External Program Bus Cycle - Read Waveforms ALE TLHLL TPLPH TLLPL PSEN TPLIV TPLAZ TAVLL TLLAX P0 D7:0 TPXAV TPXIZ TPXIX A7:0 D7:0 A7:0 D7:0 Instruction In P2 24.3.2 24.3.2.1 Instruction In A15:8 A15:8 External Data 8-bit Bus Cycles Definition of Symbols Table 24-11. External Data 8-bit Bus Cycles Timing Symbol Definitions Signals 24.3.2.
AT8xC51SND2C/MP3B Variable Clock Standard Mode Symbol Parameter TRLRH RD Pulse Width TRHLH RD high to ALE High TAVDV Address Valid to Valid Data In TAVRL Address Valid to RD Low TRLDV RD Low to Valid Data TRLAZ RD Low to Address Float TRHDX Data Hold After RD High TRHDZ Instruction Float After RD High Min Max 6·TCLCL-25 TCLCL-20 Variable Clock X2 Mode Min Max 3·TCLCL-25 TCLCL+20 0.5·TCLCL-20 9·TCLCL-65 4·TCLCL-30 Unit ns 0.5·TCLCL+20 ns 4.
24.3.2.3 Waveforms Figure 24-15. External Data 8-bit Bus Cycle - Read Waveforms ALE TLHLL TLLRL TRLRH TRHLH RD TRLDV TRHDZ TRLAZ TAVLL P0 TLLAX TRHDX A7:0 D7:0 TAVRL Data In TAVDV P2 A15:8 Figure 24-16. External Data 8-bit Bus Cycle - Write Waveforms ALE TLHLL TLLWL TWHLH TWLWH WR TAVWL TAVLL P0 TLLAX TQVWH A7:0 TWHQX D7:0 Data Out P2 24.3.3 24.3.3.1 A15:8 External IDE 16-bit Bus Cycles Definition of Symbols Table 24-14.
AT8xC51SND2C/MP3B 24.3.3.2 Timings Test conditions: capacitive load on all pins= 50 pF. Table 24-15. External IDE 16-bit Bus Cycle - Data Read AC Timings VDD = 2.7 to 3.3 V, TA = -40 to +85°C Variable Clock Standard Mode Symbol Parameter TCLCL Clock Period TLHLL ALE Pulse Width TAVLL Min Max Variable Clock X2 Mode Min Max Unit 50 50 ns 2·TCLCL-15 TCLCL-15 ns Address Valid to ALE Low TCLCL-20 0.5·TCLCL-20 ns TLLAX Address hold after ALE Low TCLCL-20 0.
24.3.3.3 Waveforms Figure 24-17. External IDE 16-bit Bus Cycle - Data Read Waveforms ALE TLHLL TLLRL TRLRH TRHLH RD TRLDV TRHDZ TRLAZ TAVLL P0 TLLAX TRHDX A7:0 D7:0 TAVRL Data In TAVDV P2 D15:8(1) A15:8 Data In Note: 1. D15:8 is written in DAT16H SFR. Figure 24-18. External IDE 16-bit Bus Cycle - Data Write Waveforms ALE TLHLL TLLWL TWLWH TWHLH WR TAVWL TAVLL P0 TLLAX TQVWH A7:0 TWHQX D7:0 Data Out P2 D15:8(1) A15:8 Data Out Note: 24.4 1.
AT8xC51SND2C/MP3B 24.4.0.5 Timings Test conditions: capacitive load on all pins= 50 pF. Table 24-18. SPI Interface Master AC Timing VDD = 2.7 to 3.3 V, TA = -40 to +85°C Symbol Parameter Min Max Unit Slave Mode TCHCH Clock Period 2 TPER TCHCX Clock High Time 0.8 TPER TCLCX Clock Low Time 0.
24.4.0.6 Waveforms Figure 24-19. SPI Slave Waveforms (SSCPHA= 0) SS (input) TSLCH TSLCL TCHCH SCK (SSCPOL= 0) (input) TCHCX TSHSL TCLCX TCHCL SCK (SSCPOL= 1) (input) TCLOX TCHOX TCLOV TCHOV TSLOV MISO (output) TCLCH TCLSH TCHSH SLAVE MSB OUT BIT 6 TSHOX SLAVE LSB OUT (1) TIVCH TCHIX TIVCL TCLIX MOSI (input) Note: MSB IN BIT 6 LSB IN 1. Not Defined but generally the MSB of the character which has just been received. Figure 24-20.
AT8xC51SND2C/MP3B Figure 24-21. SPI Master Waveforms (SSCPHA= 0) SS (output) TCHCH SCK (SSCPOL= 0) (output) TCHCX TCLCH TCLCX TCHCL SCK (SSCPOL= 1) (output) TIVCH TCHIX TIVCL TCLIX MOSI (input) MSB IN BIT 6 LSB IN TCLOX TCLOV TCHOV MISO (output) Note: Port Data MSB OUT TCHOX BIT 6 LSB OUT Port Data 1. SS handled by software using general purpose port pin. Figure 24-22.
24.4.1 24.4.1.1 Two-wire Interface Timings Table 24-19. TWI Interface AC Timing VDD = 2.7 to 3.3 V, TA = -40 to +85°C INPUT Min Max OUTPUT Min Max Start condition hold time 14·TCLCL(4) 4.0 µs(1) TLOW SCL low time 16·TCLCL(4) 4.7 µs(1) THIGH SCL high time 14·TCLCL(4) 4.0 µs(1) TRC SCL rise time 1 µs -(2) TFC SCL fall time 0.3 µs 0.
AT8xC51SND2C/MP3B 24.4.1.2 Waveforms Figure 24-23. Two Wire Waveforms Repeated START condition START or Repeated START condition START condition Tsu;STA STOP condition Trd 0.7 VDD 0.3 VDD SDA (INPUT/OUTPUT) Tsu;STO Tfd Trc Tfc 0.7 VDD 0.3 VDD SCL (INPUT/OUTPUT) Thd;STA 24.4.2 24.4.2.1 Tlow Thigh Tsu;DAT1 Tsu;DAT2 Thd;DAT MMC Interface Definition of symbols Table 24-20. MMC Interface Timing Symbol Definitions Signals 24.4.2.
24.4.2.3 Waveforms Figure 24-24. MMC Input-Output Waveforms TCHCH TCHCX TCLCX MCLK TCHCL TCLCH TCHIX TIVCH MCMD Input MDAT Input TCHOX TOVCH MCMD Output MDAT Output 24.4.3 24.4.3.1 Audio Interface Definition of symbols Table 24-22. Audio Interface Timing Symbol Definitions Signals 24.4.3.2 Conditions C Clock H High O Data Out L Low S Data Select V Valid X No Longer Valid Timings Table 24-23. Audio Interface AC timings VDD = 2.7 to 3.
AT8xC51SND2C/MP3B 24.4.3.3 Waveforms Figure 24-25. Audio Interface Waveforms TCHCH TCHCX TCLCX DCLK TCHCL TCLCH TCLSV DSEL Right Left TCLOV DDAT 24.4.4 24.4.4.1 Flash Memory Definition of symbols Table 24-24. Flash Memory Timing Symbol Definitions Signals 24.4.4.2 Conditions S ISP L Low R RST V Valid B FBUSY flag X No Longer Valid Timings Table 24-25. Flash Memory AC Timing VDD = 2.7 to 3.
24.4.4.3 Waveforms Figure 24-26. FLASH Memory - ISP Waveforms RST TSVRL ISP Note: TRLSX (1) 1. ISP must be driven through a pull-down resistor (see Section “In System Programming”, page 218). Figure 24-27. FLASH Memory - Internal Busy Waveforms FBUSY bit 24.4.5 24.4.5.1 TBHBL External Clock Drive and Logic Level References Definition of symbols Table 24-26. External Clock Timing Symbol Definitions Signals C 24.4.5.2 Conditions Clock H High L Low X No Longer Valid Timings Table 24-27.
AT8xC51SND2C/MP3B 24.4.5.3 Waveforms Figure 24-28. External Clock Waveform TCLCH VDD - 0.5 VIH1 TCHCX TCLCX VIL 0.45 V TCHCL TCLCL Figure 24-29. AC Testing Input/Output Waveforms INPUTS VDD - 0.5 0.45 V Note: OUTPUTS 0.7 VDD VIH min 0.3 VDD VIL max 1. During AC testing, all inputs are driven at VDD -0.5 V for a logic 1 and 0.45 V for a logic 0. 2. Timing measurements are made on all outputs at VIH min for a logic 1 and VIL max for a logic 0. Figure 24-30. Float Waveforms VLOAD VLOAD + 0.
25. Ordering Information Part Number Memory Size ADC Supply Voltage Range Max Frequency (MHz) Package Packing Temp.
AT8xC51SND2C/MP3B 26. Package Information 26.
27. Datasheet Revision History 27.1 Changes from 4341A - 10/04 to 4341B - 01/05 1. Update Power Amplifier DC characteristics, Section “Electrical Characteristics”, page 207. 2. Fix minor bugs. 3. Update power consumption measures, Table 24-2 on page 208. 27.2 Changes from 4341B - 01/05 to 4341C - 03/05 1. Change to hardware security system description. Section “Hardware Security System”, page 20. 27.3 Changes from 4341C - 03/05 to 4341D - 04/05 1. Update to DAC gain information, Figure 15-2 on page 82.
AT8xC51SND2C/MP3B 27.5 Changes from 4341E - 06/05 to 4341F - 03/06 1. Added 8xSND2CxxxMP3B description with A/D converter. 27.6 Changes from 4341F - 03/05 to 4341G - 07/07 1. Updated Package drawing for CTBGA100. “CTBGA100” on page 235. 27.7 Changes from 4341G - 07/07 to 4341H - 10/07 1. Added part number AT89C51SND2C-7FTUL to ordering information. 2. Modified address in the PSW register, Table 7-4 on page 29.
1. Description ............................................................................................... 2 2. Typical Applications ................................................................................ 2 3. Block Diagram .......................................................................................... 3 4. Pin Description ......................................................................................... 4 4.1 Pinouts ....................................................
AT8xC51SND2C/MP3B 10.2 Reset Recommendation to Prevent Flash Corruption .......................................... 48 10.3 Idle Mode.............................................................................................................. 49 10.4 Power-down Mode ............................................................................................... 49 10.5 Registers .............................................................................................................. 51 11.
15.1 DAC ...................................................................................................................... 81 15.2 Power Amplifier .................................................................................................... 98 15.3 Audio Supplies and Start-up................................................................................. 99 16. Universal Serial Bus ............................................................................ 103 16.
AT8xC51SND2C/MP3B 20.1 Mode Selection................................................................................................... 168 20.2 Baud Rate Generator ......................................................................................... 168 20.3 Synchronous Mode (Mode 0) ............................................................................. 169 20.4 Asynchronous Modes (Modes 1, 2 and 3).......................................................... 171 20.
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