Datasheet

34
9502A–AT42–07/08
AT42QT2160
Shared X line GPOs are always outputs. By default, the dedicated GPIOs are set as inputs.
Make sure to drive (set to outputs) these GPIOs if not used, as floating pins may consume
unnecessary current.
Default: 0 (All inputs)
7.24 Address 74...75: GPIO/GPO PWM
Setting the corresponding GPIO PWM bit to 1 will enable PWM on the respective pin. The pin
will be driven according to the duty cycle specified in PWM Level (address 76).
PWM will only be enabled on GPIOs that have their GPIO direction set to 1 (output).
Shared X line GPOs will only be driven when not doing any measurements. During
measurements, burst pulses will be driven from the X lines, making sure that the driven device
will not be affected.
All PWM enabled GPIOs/GPOs will only be switched when not doing any measurements.
Therefore, the PWM duty cycle’s accuracy will depend on the burst lengths of keys, as the
longer the burst length, the longer the periods of no PWM switching.
Default: 0 (PWM disabled)
7.25 Address 76: PWM Level
This sets the Duty Cycle of the PWM enabled pins. Valid values are between 0 to 255. A value
of 0...10 will be 100 percent duty cycle (always on), and a value of 250...255 will be 0 percent
duty cycle (always off).
Default: 0 (100 percent duty cycle)
Table 7-25. GPIO/GPO PWM
Addressb7b6b5b4b3b2b1b0
74 X7 X6 X5 X4 X3 X2 X1 X0
75 0 0 0 GPIO3 GPIO2 GPIO1 0 0
Table 7-26. PWM Level
Addressb7b6b5b4b3b2b1b0
76 DUTY_CYC