Datasheet

25
9502A–AT42–07/08
AT42QT2160
7.4 Address 2: General Status
These bits indicate the general status of the device. A change in this byte will cause the
CHANGE
line to trigger.
RESET: this bit is set after a reset. This bit is clear after this byte is read back by the host.
CYCLE OVERRUN: this bit is set if the cycle time is more than 16ms. It will be cleared when the
cycle time is less than 16ms.
Note: holding any of the
I
2
C-compatible lines, for clock stretching or other purposes, will
increase the cycle time.
CC: this common change bit is set if all the selected keys (address 78...79) have a signal
change of more than half the detection threshold, NTHR. The CC bit is not debounced.
This bit can be used to indicate a common change in signals, e.g. In a notebook application,
where the cover is closing, so that the host can suppress key detections.
Note: the CC bit will be set to 1 if no keys are selected to be in the Common Change group (see
Section 7.27 on page 35).
SDET: this bit is set if a touch is detected on the slider.
7.5 Address 3...4: Key Status
Address 3: detect status for keys 0 to 7
Address 4: detect status for keys 8 to 15
Each location indicates all keys in detection, if any, as a bitfield; touched keys report as “1”,
untouched or disabled keys report as “0”. A change in this byte will cause the CHANGE
line to
trigger.
Table 7-4. General Status
Addressb7b6b5b4b3b2b1b0
2 RESET
CYCLE
OVER
RUN
0 0 0 0 CC SDET
Table 7-5. Key Status and Numbering
Addressb7b6b5b4b3b2b1b0
3 k7k6k5k4k3k2k1k0
4 k15k14k13k12k11k10 k9 k8