Datasheet

23
9502A–AT42–07/08
AT42QT2160
7. Communications Protocol
7.1 Introduction
The device is address mapped. All communications consist of writes to, and reads from,
locations in an 8-bit address map. Table 7-1 shows the address map of QT2160.
Table 7-1. Memory Map
Address Use Access
0 Chip ID Read
1 Major/minor code version Read
2 General Status Read
3 Key Status 1 Read
4 Key Status 2 Read
5 Slider Touch Position Read
6 GPIO Read Read
7 Sub-revision -
8...9 Reserved - 0x00 -
10 Calibrate Read/Write
11 Reset Read/Write
12 LP Mode Read/Write
13 Burst Repetition Read/Write
14 Reserved - 0x00 Read/Write
15 Neg Drift Compensation Read/Write
16 Pos Drift Compensation Read/Write
17 Normal DI Limit Read/Write
18 Neg Recal Delay Read/Write
19 Drift Hold Time/AWAKE Read/Write
20 Slider Control Read/Write
21 Slider Options Read/Write
22...37 Key 0 - 15 Key Control Read/Write
38...53 Key 0 - 15 Neg Threshold Read/Write
54...69 Key 0 - 15 Burst Length Read/Write
70 GPIO/GPO Drive 1 Read/Write