Datasheet

21
9502A–AT42–07/08
AT42QT2160
6. Interfaces
6.1 I
2
C-compatible Protocol
The I
2
C-compatible protocol is based around access to an address table and supports multibyte
reads and writes.
Note: Each write or read cycle must end with a stop condition. The QT2160 may not respond
correctly if a cycle is terminated by a new start condition.
6.2 I
2
C-compatible Addresses
Four preset I
2
C-compatible addresses are selectable through pin I2CA0 and I2CA1 (Table 6-1).
6.3 Data Read/Write
6.3.1 Writing Data to the Device
The sequence of events required to write data to the device is shown next.
The host initiates the transfer by sending the START condition, and follows this by sending the
slave address of the device together with the Write-bit. The device sends an ACK. The host then
sends the memory address within the device it wishes to write to. The device sends an ACK.
The host transmits one or more data bytes; each will be acknowledged by the device.
Table 6-1.
I
2
C-compatible Addresses
I2CA1 I2CA0 Address
000x0D
0 1 0x17
1 0 0x44
110x6B
Key
S Start condition
SLA+W Slave address plus write bit
A Acknowledge bit
MemAddress Target memory address within device
Data Data to be written
P Stop condition
SLA+W
MemAddress
AAS
Data A P
Host to Device Device to Host