Datasheet

9502A–AT42–07/08

AT42QT2160

Figure 5-4. Address Packet Format

5.5 Data Packet Format

All data packets are 9 bits long, consisting of one data byte and an acknowledge bit. During a

data transfer, the host generates the clock and the START and STOP conditions, while the

Receiver is responsible for acknowledging the reception. An acknowledge (ACK) is signaled by

the Receiver pulling the SDA line low during the ninth SCL cycle. If the Receiver leaves the SDA

line high, a NACK is signaled.

5.6 Combining Address and Data Packets Into a Transmission

A transmission consists of a START condition, an SLA+R/W, one or more data packets and a

STOP condition. The wired-ANDing of the SCL line is used to implement handshaking between

the host and the device. The device extends the SCL low period by pulling the SCL line low

whenever it needs extra time for processing between the data transmissions.

Holding down either SCL or SDA for clock stretching or any other purpose will slow down the

operation of the QT2160. If SCL or SDA is continuously held low for more than ~12ms, this will

be deemed as a error condition and the

C-compatible unit reset.

Note: Each write or read cycle must end with a STOP condition. The QT2160 may not respond

correctly if a cycle is terminated by a new START condition.

SDA

SCL

Addr MSB Addr LSB R/W ACK

TART

12 789