Datasheet

17
9502A–AT42–07/08
AT42QT2160
5. I
2
C-compatible Bus Operation
5.1 Interface Bus
More detailed information about the I
2
C-compatible bus protocol is available from
www.i2C-bus.org. Devices are connected onto the
I
2
C-compatible bus as shown in Figure 5-1.
Both bus lines are connected to Vdd via pull-up resistors. The bus drivers of all
I
2
C-compatible
devices must be open-drain type. This implements a wired-AND function which allows any and
all devices to drive the bus, one at a time. A low level on the bus is generated when a device
outputs a zero.
Figure 5-1.
I
2
C-compatible Interface Bus
5.2 Transferring Data Bits
Each data bit transferred on the bus is accompanied by a pulse on the clock line. The level of the
data line must be stable when the clock line is high; The only exception to this rule is for
generating START and STOP conditions.
Table 5-1.
I
2
C-compatible Bus Specifications
Parameter Unit
Address space 7-bit
Maximum bus speed (SCL) 100 kHz
Hold time START condition 4 µs minimum
Setup time for STOP condition 4 µs minimum
Bus free time between a STOP and START condition 4.7 µs minimum
Rise times on SDA and SCL 1 µs maximum
Vdd
Device 1 Device 2 Device 3 Device n R1 R2
SDA
SCL