Datasheet

12
9502A–AT42–07/08
AT42QT2160
Caution: A regulator IC shared with other logic devices can result in erratic operation and is not
advised.
A regulator can be shared among two or more QT devices on one board. Refer to page 15 for
suggested regulator manufacturers.
A single ceramic 0.1uF bypass capacitor, with short traces, should be placed very close to
supply pins 3 and 4 of the IC. Failure to do so can result in device oscillation, high current
consumption, erratic operation etc. Pins 16 and 17 do not require bypassing if the traces
between these pins and power traces are short.
4.12 Startup/Calibration Times
The device requires initialization times of approximately 70ms. The CHANGE line will go low and
calibration will start (takes 15 matrix scans), after this start up period is over.
4.13 Calibration
Calibration does not occur periodically. Keys are only calibrated on power-up and when:
•Enabled
AND
– held in detect for too long. The negative recalibration delay (NRD) period is specified
by the user
OR
– the signal delta value is greater than the positive threshold value, defined as
reference value plus three-quarters of the negative threshold
OR
– the user issues a recalibrate command
An interrupt on the CHANGE
pin occurs when there is a change in the key status bytes. An
interrupt will occur on calibration only if at least one of the keys or objects was in detect as
recalibration will then cause a status change.
4.14 Reset Input
The RST pin can be used to reset the device to simulate a power-down cycle, in order to bring
the device up into a known state should communications with the device be lost. The pin is
active low, and a low pulse lasting at least 10µs must be applied to this pin to cause a reset.
If an external hardware reset is not used, the reset pin may be connected to Vdd.