Datasheet

AT30TSE752A/754A/758A [DATASHEET]

Atmel-8854G-DTS-AT30TSE752A-754A-758A-Datasheet_102014

4. Device Communication

The AT30TSE752A/754A/758A operates as a slave device and utilizes a simple 2-wire I

C and SMBus compatible digital

serial interface to communicate with a host controller, commonly referred to as the bus Master. The Master initiates and

controls all Read and Write operations to the slave devices on the serial bus, and both the Master and the slave devices

can transmit and receive data on the bus.

The serial interface is comprised of just two signal lines: Serial Clock (SCL) and Serial Data (SDA). The SCL pin is used

to receive the clock signal from the Master, while the bidirectional SDA pin is used to receive command and data

information from the Master as well as to send data back to the Master. Data is always latched into the

AT30TSE752A/754A/758A on the rising edge of SCL and always output from the device on the falling edge of SCL. Both

the SCL and SDA pin incorporate integrated spike suppression filters and Schmitt triggers to minimize the effects of input

spikes and bus noise.

All command and data information is transferred with the Most-Significant Bit (MSB) first. During bus communication, one

data bit is transmitted every clock cycle, and after eight bits (one byte) of data has been transferred, the receiving device

must respond with either an acknowledge (ACK) or a no-acknowledge (NACK) response bit during a ninth clock cycle

(ACK/NACK clock cycle) generated by the Master. Therefore, nine clock cycles are required for every one byte of data

transferred. There are no unused clock cycles during any Read or Write operation, so there must not be any interruptions

or breaks in the data stream during each data byte transfer and ACK or NACK clock cycle.

During data transfers, data on the SDA pin must only change while SCL is low, and the data must remain stable while

SCL is high. If data on the SDA pin changes while SCL is high, then either a Start or a Stop condition will occur. Start and

Stop conditions are used to initiate and end all serial bus communication between the Master and the slave devices. The

number of data bytes transferred between a Start and a Stop condition is not limited and is determined by the Master.

In order for the serial bus to be idle, both the SCL and SDA pins must be in the logic-high state at the same time.

4.1 Start Condition

A Start condition occurs when there is a high-to-low transition on the SDA pin while the SCL pin is stable in the logic-high

state. The Master uses a Start condition to initiate any data transfer sequence, and the Start condition must precede any

command. The AT30TSE752A/754A/758A will continuously monitor the SDA and SCL pins for a Start condition, and the

device will not respond unless one is given.

4.2 Stop Condition

A Stop condition occurs when there is a low-to-high transition on the SDA pin while the SCL pin is stable in the logic-high

state. The Master uses the Stop condition to end a data transfer sequence to the AT30TSE752A/754A/758A which will

subsequently return to the idle state. The Master can also utilize a repeated Start condition instead of a Stop condition to

end the current data transfer if the Master will perform another operation.

4.3 Acknowledge (ACK)

After every byte of data received, the AT30TSE752A/754A/758A must acknowledge to the Master that it has successfully

received the data byte by responding with an ACK. This is accomplished by the Master first releasing the SDA line and

providing the ACK/NACK clock cycle (a ninth clock cycle for every byte). During the ACK/NACK clock cycle, the

AT30TSE752A/754A/758A must output a Logic 0 (ACK) for the entire clock cycle such that the SDA line must be stable

in the logic-low state during the entire high period of the clock cycle.