Datasheet

AT30TSE752A/754A/758A [DATASHEET]
Atmel-8854G-DTS-AT30TSE752A-754A-758A-Datasheet_102014
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10.4.3 Sequential Read
Sequential Read operations are initiated in the same way as a Random Read, except that after the
AT30TSE752A/754A/758A transmits the first data byte, the Master issues a ACK instead of a NACK and Stop condition
in a Random Read operation. This directs the AT30TSE752A/754A/758A to increment the internal address pointer by
one and transmit the next sequentially addressed data byte. The AT30TSE752A/754A/758A will repeat and continue
transmitting sequential data bytes until the Master wants to terminate the Read operation by issuing a NACK and Stop
condition.
Figure 10-5. Sequential Read from Serial EEPROM
10.5 Software Write Protect
The AT30TSE752A/754A/758A features a Reversible Software Write Protect (RSWP) mode that once enabled, disables
the Serial EEPROM write circuitry and therefore, protects the contents of the entire memory array against any intentional
or unintentional Write operations. The RSWP feature is invoked by sending the “Set RSWP” protocol sequence to the
AT30TSE752A/754A/758A that is similar to a normal memory Write command sequence as shown in Table 10-3 and
Figure 10-6. The Master can set the memory array to Full Write Protection status by issuing a Start condition followed by
01100010 (62h) and the AT30TSE752A/754A/758A will respond with an ACK. Next, the Master sends the word address
byte and the AT30TSE752A/754A/758A will respond with an ACK. Then the Master sends the data byte and the
AT30TSE752A/754A/758A will respond with an ACK. The word address and data bytes are don't care values. In
addition, during the protocol sequence, the A
2
and A
1
device address pins must be set to ground and the A
0
device
address pin set to V
HV
.
The Software Write Protection can be reversed to no protect status by the Master sending the “Clear RSWP” protocol
sequence as shown in Table 10-3 and Figure 10-7. This requires the Master to send a Start condition followed by
01100110 (66h), Word Address Byte, Data Byte, and a Stop condition with an ACK response from the
AT30TSE752A/754A/758A after each byte transferred. The word address and data bytes are don't care values. In
addition, during the protocol sequence, the A
2
device address pin must be set to ground, A
1
device address pin set to
V
CC
and the A
0
device address pin set to V
HV
.
SCL
SDA
Start
by
Master
ACK
from
Slave
ACK
from
Master
Device Address Byte Data Byte (n)
MSB MSB
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
1 0 1 0 A A/P1 A/P0 1 0 D7 D6 D5 D4 D3 D2 D1 D0 0
ACK
from
Master
NACK
from
Master
Stop
by
Master
ACK
from
Master
Data Byte (n+1) Data Byte (n+2)
Data Byte (n+x)
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
D7 D6 D5 D4 D3 D2 D1 D0 0 D7 D6 D5 D4 D3 D2 D1 D0 0 D7 D6 D5 D4 D3 D2 D1 D0 1
MSB MSB MSB