Datasheet

AT30TSE752A/754A/758A [DATASHEET]
Atmel-8854G-DTS-AT30TSE752A-754A-758A-Datasheet_102014
38
Figure 10-2. Page Write to Serial EEPROM
10.3.3 Acknowledge Polling
Since the AT30TSE752A/754A/758A will NACK during a write cycle because it is busy writing data, this can be used to
determine when the write cycle is complete and therefore could be used to maximize bus throughput. Once the Stop
condition for a write sequence has been issued from the Master, the AT30TSE752A/754A/758A initiates the internally
self-timed write cycle and ACK polling can then be immediately started by the Master. This involves the Master
transmitting a Start condition followed the device address byte. If the AT30TSE752A/754A/758A is still busy with the
write cycle, NACK will be returned by the device. If the write cycle is complete, the device will ACK indicating the write
cycle is complete and the Master can then proceed with the next Read or Write operation.
10.4 Read Operations
Read operations are initiated in the same way as Write operations, with the exception that the R/W is set to a Logic 1
state. There are three basic types of Read operations:
 Current Address Read
 Random Read
 Sequential Read
10.4.1 Current Address Read
The AT30TSE752A/754A/758A contains an internal address counter that maintains the address of the last byte address
accessed during the last Read or Write operation incremented by one. The address stays valid between operations as
long as the power to the device is maintained. The address rollover during a Read operation is from the last byte of the
last memory page to the first byte of the first page. Upon receipt of the device address byte with the R/
W bit set to a Logic
1 state, the AT30TSE752A/754A/758A will ACK and transmit the 8-bit data byte. The Master will respond with a NACK
followed by a Stop condition to end the transmission. It is recommended to not rely on the Current Address Read
operation because the only way to guarantee the correct Read Address is to use the Random Read Protocol that loads
the specific starting byte address location of the data to be read. For more details about the Random Read Protocol, see
Section 10.4.2, Random Read.
SCL
SDA
Start
by
Master
ACK
from
Slave
ACK
from
Slave
Device Address Byte Word Address Byte
MSB MSB
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
1 0 1 0 A A/P1 A/P0 0 0 0 0 0 0 0 0 0 0 0
ACK
from
Slave
ACK
from
Slave
Stop
by
Master
ACK
from
Slave
Data Byte (n) Data Byte (n+1)
Data Byte (n+15)
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
D7 D6 D5 D4 D3 D2 D1 D0 0 D7 D6 D5 D4 D3 D2 D1 D0 0 D7 D6 D5 D4 D3 D2 D1 D0 0
MSB MSB MSB