Datasheet
AT30TSE752A/754A/758A [DATASHEET]
Atmel-8854G-DTS-AT30TSE752A-754A-758A-Datasheet_102014
28
ready for the lower byte of data. The AT30TSE752A/754A/758A will then clock out the lower byte of the register, after
which the Master must send a NACK to end the operation. When the AT30TSE752A/754A/758A receives the NACK, it
will release the SDA line so that the Master can send a Stop or repeated Start condition. If the Master does not send a
NACK but instead sends an ACK after the lower byte of the register has been clocked out, then the device will repeat the
sequence by outputting the data again starting with the upper byte of the register.
After the device powers up or resets, both the T
LOW
and T
HIGH
Limit Register values will be copied from the Nonvolatile
T
LOW
and T
HIGH
Limit Registers; therefore, the T
LOW
and T
HIGH
Limit Register values will default to whatever value was
previously stored in the Nonvolatile T
LOW
and T
HIGH
Limit Registers prior to power-down or reset. The value of the high
temperature limit stored in the T
HIGH
Limit Register must be greater than the value of the low temperature limit stored in
the T
LOW
Limit Register in order for the ALERT function to work properly; otherwise, the ALERT pin will output erroneous
results and will falsely signal temperature alarms.
Figure 6-8. Write to T
LOW
or T
HIGH
Limit Register
Figure 6-9. Read from T
LOW
or T
HIGH
Limit Register
Note: Assumes the Pointer Register was previously set to point to the T
LOW
or T
HIGH
Limit Register.
SCK
SDA
Start
by
Master
ACK
from
Slave
ACK
from
Slave
Address Byte
T
LOW
or T
HIGH
Limit Register
Upper Byte
T
LOW
or T
HIGH
Limit Register
Lower Byte
Pointer Register Byte
MSB MSB
ACK
from
Slave
ACK
from
Slave
Stop
by
Master
MSB MSB
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
1 0 0 1 A A A 0 0 0 0 0 0 0 0 P1 P0 0
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
D15 D14 D13 D12 D11 D10 D9 D8 0 D7 D6 D5 D4 D3 D2 D1 D0 0
SCK
SDA
Start
by
Master
ACK
from
Slave
NACK
from
Master
Stop
by
Master
ACK
from
Master
Address Byte
T
LOW
or T
HIGH
Limit Register
Upper Byte
T
LOW
or T
HIGH
Limit Register
Lower Byte
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
1 0 0 1 A A A 1 0 D15 D14 D13 D12 D11 D10 D9 D8 0 D7 D6 D5 D4 D3 D2 D1 D0 1
MSB MSB MSB