Datasheet

27
AT30TSE752A/754A/758A [DATASHEET]
Atmel-8854G-DTS-AT30TSE752A-754A-758A-Datasheet_102014
6.5 T
LOW
and T
HIGH
Limit Registers
The 16-bit T
LOW
and T
HIGH
Limit Registers store the user-programmable lower and upper temperature limits for the
temperature alarm. Like the Temperature Register, the temperature data values of the T
LOW
and T
HIGH
Limit Registers
are stored in the twos complement format with the MSB (bit 15) of the registers containing the sign bit (zero indicates a
positive number and a one indicates a negative number).
As with the Temperature Register, the resolution selected by the R1 and R0 bits of the Configuration Register will
determine how many bits of the T
LOW
and T
HIGH
Limit Registers will be used; therefore, when writing to the T
LOW
and
T
HIGH
Limit Registers, up to 12 bits of data will be recognized by the device with the remaining LSBs being internally fixed
to the Logic 0 state. Similarly, when reading from the registers, up to 12 bits of data will be output from the device with the
remaining LSBs fixed in the Logic 0 state.
Table 6-11. T
LOW
Limit Register and T
HIGH
Limit Register Format
Note: TD = Temperature Data
To set the value of either the T
LOW
or T
HIGH
Limit Register, the Master must first initiate a Start condition followed by the
AT30TSE752A/754A/758A device address byte (1001AAA0 where “AAA” corresponds to the hard-wired A
2-0
address
pins). After the AT30TSE752A/754A/758A has received the proper address byte, the device will send an ACK to the
Master. The Master must then send the appropriate Pointer Register byte of 02h to select the T
LOW
Limit Register or 03h
to select the T
HIGH
Limit Register. After the Pointer Register byte has been sent, the AT30TSE752A/754A/758A will send
another ACK to the Master. After receiving the ACK from the AT30TSE752A/754A/758A, the Master must then send two
data bytes to the AT30TSE752A/754A/758A to set the value of the T
LOW
or T
HIGH
Limit Register. Any subsequent bytes
sent to the AT30TSE752A/754A/758A will simply be ignored by the device. If the Master does not send two complete
bytes of data prior to issuing a Stop or repeated Start condition, then the AT30TSE752A/754A/758A will ignore the data
and the contents of the register will not be changed.
In addition to the Master not sending two complete bytes of data, writing to the T
LOW
or T
HIGH
Limit Register will be
ignored and no operation will be performed under the following conditions: the Nonvolatile Registers are busy because of
a copy operation (the NVRBSY bit of the Configuration Register is in the Logic 1 state), the Volatile and Nonvolatile
Registers are currently locked (the RLCK bit of the Nonvolatile Configuration Register is in the Logic 1 state), or the
Volatile and Nonvolatile Registers are permanently locked down (the RLCKDWN bit of the Nonvolatile Configuration
Register is in the Logic 1 state). However, the device will still respond with an ACK, except in the case of the Nonvolatile
Registers being busy, to indicate that it received the proper data bytes even though the contents of the T
LOW
or T
HIGH
Limit Register will not be changed. In the case of the Nonvolatile Registers being busy, the device will respond with an
ACK to the address and pointer bytes but will then NACK when the data bytes are sent from the Master.
In order to read the T
LOW
or T
HIGH
Limit Register, the Pointer Register must be set or have been previously set to 02h to
select the T
LOW
Limit Register or 03h to select the T
HIGH
Limit Register (if the previous operation was a Write to one of the
registers, then the Pointer Register will already be set for that particular limit register). If the Pointer Register has already
been set appropriately, the T
LOW
or T
HIGH
Limit Register can be read by having the Master first initiate a Start condition
followed by the AT30TSE752A/754A/758A device address byte (1001AAA1 where “AAA” corresponds to the hard-wired
A
2-0
address pins). After the AT30TSE752A/754A/758A has received the proper address byte, the device will send an
ACK to the Master. The Master can then read the upper byte of the T
LOW
or T
HIGH
Limit Register. After the upper byte of
the register has been clocked out of the AT30TSE752A/754A/758A, the Master must send an ACK to indicate that it is
Resolution
Upper Byte Lower Byte
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
12 bits Sign TD TD TD TD TD TD TD TD TD TD TD 0 0 0 0
11 bits Sign TD TD TD TD TD TD TD TD TD TD 0 0 0 0 0
10 bits Sign TD TD TD TD TD TD TD TD TD 0 0 0 0 0 0
9 bits Sign TD TD TD TD TD TD TD TD 0 0 0 0 0 0 0