Datasheet

25
AT30TSE752A/754A/758A [DATASHEET]
Atmel-8854G-DTS-AT30TSE752A-754A-758A-Datasheet_102014
6.4.2 NVFT1:NVFT0 Bits
The nonvolatile NVFT1 and NVFT0 bits are used to set the power-up/reset default Fault Tolerance Queue value which
defines how many consecutive faults must occur before the ALERT pin will be activated (see Section 5.2.1, “Fault
Tolerance Limits” on page 11). The NVFT1 and NVFT0 bit settings provide four different fault values as detailed in
Table 6-10. Both the NVFT1 and NVFT0 bits are factory-set to default to the Logic 0 state.
Table 6-10. Fault Tolerance Queue
6.4.3 NVPOL Bit
The nonvolatile NVPOL bit controls the power-up/reset default ALERT pin polarity. When the NVPOL bit is set to the
Logic 0 state, the ALERT pin will be an active low output after the device powers up or resets. Conversely, when the
NVPOL bit is set to the Logic 1 state, the ALERT pin will be an active high output. The NVPOL bit is set from the factory
to default to the Logic 0 state.
6.4.4 NVCMP/INT Bit
The nonvolatile NVCMP/INT bit controls whether the device will operate in the Comparator mode or the Interrupt mode
after a power-up or reset sequence. Setting the NVCMP/INT bit to the Logic 0 state (the factory default setting) will allow
the device to power-up/reset in the Comparator mode. Alternatively, when the NVCMP/INT bit is set to the Logic 1 state,
the device will power-up/reset in the Interrupt mode.
6.4.5 NVSD Bit
The nonvolatile NVSD bit is used to enable the device to power-up/reset in the Shutdown mode. When the NVSD bit is in
the Logic 0 state, the device will power-up/reset in the normal operational mode and perform continuous temperature
measurements and conversions. When the NVSD bit is set to the Logic 1 state, the device will automatically enter the
Shutdown mode after a power-up or reset sequence (see Section 5.3, “Shutdown Mode” on page 14 for more details).
The NVSD bit is factory-set to the Logic 0 state.
6.4.6 RLCKDWN
The one-time programmable RLCKDWN bit controls whether or not both the volatile and nonvolatile versions of the
configuration and limit registers will be permanently locked down. Once the RLCKDWN bit is set to the Logic 1 state, the
Configuration Register, T
LOW
Limit Register, T
HIGH
Limit Register, Nonvolatile Configuration Register, Nonvolatile T
LOW
Limit Register, and Nonvolatile T
HIGH
Limit Register will be locked down and can never be modified again. Since the
RLCKDWN bit is one-time programmable, once the bit is set to the Logic 1 state, it cannot be reset again. The
RLCKDWN bit takes priority over the RLCK bit (see Section 7., “Register Locking” on page 32 for more details) and is
factory-set to the Logic 0 state.
NVFT1 NVFT0 Consecutive Faults Required
0 0 1
0 1 2
1 0 4
1 1 6