Datasheet

AT30TSE752A/754A/758A [DATASHEET]
Atmel-8854G-DTS-AT30TSE752A-754A-758A-Datasheet_102014
22
6.3.7 NVRBSY
The Ready/Busy status of the Nonvolatile Configuration Register, Nonvolatile T
LOW
Limit Register, and Nonvolatile T
HIGH
Limit Register can be determined by reading the NVRBSY bit. When the NVRBSY bit is in the Logic 0 state, then the
Nonvolatile Configuration and Limit Registers are available to be read from or written to. When the NVRBSY bit is in the
Logic 1 state, the Nonvolatile Registers are busy and cannot be accessed for reading, writing, or copying. Attempting to
read the Nonvolatile Registers while the registers are busy will result in erroneous data being output. Similarly, any
attempts to write to one of the Nonvolatile Registers while the NVRBSY bit is in the Logic 1 state will result in the data
being ignored. Both the copy Nonvolatile Registers to Volatile Registers and the copy Volatile Registers to Nonvolatile
Registers commands will also be ignored when the NVRBSY bit is in the Logic 1 state. For more details and a complete
list of commands that are and are not allowed while NVRBSY is in the Logic 1 state, see Section 8., “Operations Allowed
During Nonvolatile Busy Status” on page 33.
Figure 6-4. Write to Configuration Register
Figure 6-5. Read from Configuration Register
Note: Assumes the Pointer Register was previously set to point to the Configuration Register.
SCK
SDA
Address Byte Pointer Register Byte Configuration Register Upper Byte
Start
by
Master
ACK
from
Slave
ACK
from
Slave
MSB
MSB
ACK
from
Slave
Stop
by
Master
MSB
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
1 0 0 1 A A A 0 0 0 0 0 0 0 0 0 1 0 D15 D14 D13 D12 D11 D10 D9 D8 0
SCK
SDA
Start
by
Master
ACK
from
Slave
NACK
from
Master
Address Byte
Configuration Register Upper Byte
Stop
by
Master
MSB MSB
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
1 0 0 1 A A A 1 0 D15 D14 D13 D12 D11 D10 D9 D8 1