Datasheet

21
AT30TSE752A/754A/758A [DATASHEET]
Atmel-8854G-DTS-AT30TSE752A-754A-758A-Datasheet_102014
6.3.3 FT1:FT0 Bits
The FT1 and FT0 bits are used to set the fault tolerance queue value which defines how many consecutive faults must
occur before the ALERT pin will be activated (see Section 5.2.1, “Fault Tolerance Limits” on page 11). The FT1 and FT0
bit settings provide four different fault values as detailed in Table 6-7. After the device powers up or resets, the FT1 and
FT0 bits will be copied from the NVFT1 and NVFT0 in the Nonvolatile Configuration Register; therefore, the fault
tolerance queue value will default to whatever value was previously stored in the Nonvolatile Configuration Register prior
to Configuration Register power-down or reset.
Table 6-7. Fault Tolerance Queue
6.3.4 POL Bit
The ALERT pin polarity is controlled by the POL bit. When the POL bit is in the Logic 0 state, the ALERT pin will be an
active low output. To configure the ALERT pin as an active high output, the POL bit must be set to the Logic 1 state.
After the device powers up or resets, the POL bit will be copied from the NVPOL bit in the Nonvolatile Configuration
Register; therefore, the polarity of the ALERT pin will default to the state defined by the Nonvolatile Configuration
Register prior to power-down or reset.
6.3.5 CMP/INT Bit
The CMP/INT bit controls whether the device will operate in the Comparator mode or the Interrupt mode. Setting the
CMP/INT bit to the Logic 0 state will put the device into the Comparator mode. Alternatively, when the CMP/INT bit is set
to the Logic 1 state, then the device will operate in the Interrupt mode. The function of the ALERT pin changes based on
the CMP/INT bit setting.
The CMP/INT bit will be copied from the NVCMP/INT bit in the Nonvolatile Configuration Register after the device powers
up or resets. Since the CMP/INT bit is copied from the NVCMP/INT bit, the device will default to whatever mode was
selected by the Nonvolatile Configuration Register prior to power-down or reset.
6.3.6 SD Bit
The SD bit is used to enable or disable the device's Shutdown mode. When the SD bit is in the Logic 0 state, the device
will be in the normal operational mode and perform continuous temperature measurements and conversions. When the
SD bit is set to the Logic 1 state, the device will finish the current temperature measurement and conversion and will
store the result in the Temperature Register, after which the device will then enter the Shutdown mode.
Resetting the SD bit back to a Logic 0 will return the device to the normal operating mode.
After the device powers up or resets, the SD bit will be copied from the NVSD bit in the Nonvolatile Configuration
Register; therefore, it is possible for the device to automatically enter the Shutdown mode after power-up or reset by
setting the NVSD bit to the Logic 1 state prior to power-down or reset. See Section 5.3, “Shutdown Mode” on page 14 for
more details.
FT1 FT0 Consecutive Faults Required
0 0 1
0 1 2
1 0 4
1 1 6