Datasheet

11
AT30TSE752A/754A/758A [DATASHEET]
Atmel-8854G-DTS-AT30TSE752A-754A-758A-Datasheet_102014
5.2 Temperature Alarm
After the measured temperature value has been stored into the Temperature Register, the data will be compared with
both the high and low temperature limits defined by the values stored in the T
HIGH
Limit Register and T
LOW
Limit Register.
If the comparison results in a valid fault condition (see Section 5.2.1, “Fault Tolerance Limits” on page 11), then the
device will activate the ALERT output pin.
The polarity and function of the ALERT pin can be configured by using specific bits in the Configuration Register. The
polarity of the ALERT pin is controlled by the POL bit in the Configuration Register while the function of the ALERT pin
changes based on the Alarm Thermostat mode, which can be configured to either Comparator mode (see Section 5.2.2,
“Comparator Mode” on page 12) or Interrupt mode (see Section 5.2.3, “Interrupt Mode” on page 13) by using the
CMP/INT bit in the Configuration Register. After the device powers up or resets, the NVPOL and NVCMP/INT bits of the
Nonvolatile Configuration Register are automatically copied into the POL and CMP/INT bits of the Configuration
Register; therefore, the ALERT pin polarity and function will revert back to the settings defined by the NVPOL and
NVCMP/INT bits prior to when the device was powered-down or reset.
The value of the high temperature limit stored in the T
HIGH
Limit Register must be greater than the value of the low
temperature limit stored in the T
LOW
Limit Register in order for the ALERT function to work properly; otherwise, the
ALERT pin will output erroneous results and will falsely signal temperature alarms.
5.2.1 Fault Tolerance Limits
A temperature fault occurs if the measured temperature meets or exceeds either the high temperature limit set by the
T
HIGH
Limit Register or the low temperature limit set by the T
LOW
Limit Register. To prevent false alarms due to
environmental or temperature noise, the device incorporates a fault tolerance queue that requires consecutive
temperature faults to occur before resulting in a valid fault condition. The fault tolerance queue value is controlled by the
FT1 and FT0 bits in the Configuration Register and can be set to a single fault count of one or a count of two, four, or six
consecutive faults.
An internal counter that automatically increments after a temperature fault is used to determine if the fault tolerance
queue setting has been met. After incrementing the fault counter, the device will compare the count to the fault tolerance
queue setting to see if a valid fault condition should be triggered. Once a valid fault condition occurs, the device will
activate the ALERT output pin. If the most recent measured temperature does not meet or exceed the high or low
temperature limit, then the internal fault counter will be reset back to zero.
Figure 5-1 shows a sample temperature profile and how each temperature fault would impact the internal fault counter.
Figure 5-1. Fault Count Example
After the device powers up or resets, the NVFT1 and NVFT0 bits of the Nonvolatile Configuration Register are
automatically copied into the FT1 and FT0 bits of the Configuration Register; therefore, the Fault Tolerance Queue
setting will revert back to the settings defined by the NVFT1 and NVFT0 bits prior to when the device was powered-down
or reset.
Temperature Measurements/Conversions
T
HIGH
Limit
Temperature
T
LOW
Limit