User manual

ATHENA CPU User Manual V1.40 Page 70
20. DATA ACQUISITION SPECIFICATIONS
These specifications apply to units with Data Acquisition Only
Analog Inputs
No. of inputs 8 differential or 16 single-ended (user selectable)
A/D resolution 16 bits (1/65,536 of full scale)
Input ranges Bipolar: ±10V, ±5V, ±2.5V, ±1.25V
Unipolar: 0-8.3V, 0-5V, 0-2.5V
Input bias current 50nA max
Maximum input voltage ±10V for linear operation
Overvoltage protection ±35V on any analog input without damage
Nonlinearity ±3LSB, no missing codes
Drift 10PPM/
o
C typical
Conversion rate 100,000 samples per second max
Conversion trigger software trigger, internal pacer clock, or external TTL signal
FIFO 48 samples; programmable interrupt threshold
Analog Outputs
No. of outputs 4
D/A resolution 12 bits (1/4096 of full scale)
Output ranges Unipolar: 0-10V or user-programmable
Bipolar: ±10V or user-programmable
Output current ±5mA max per channel
Settling time 4µS max to ±1/2 LSB
Relative accuracy ±1 LSB
Nonlinearity ±1 LSB, monotonic
Digital I/O
No. of lines 24
Compatibility 3.3V and 5V logic compatible
Input voltage Logic 0: -0.5V min, 0.8V max; Logic 1: 2.0V min, 5.5V max
Input current ±1µA max
Output voltage Logic 0: 0.0V min, 0.4V max; Logic 1: 2.4V min, 3.3V max
Output current Logic 0: 12mA max; Logic 1: -8mA max
I/O capacitance 10pF max
Counter/Timers
A/D pacer clock 24-bit down counter
Pacer clock source 10MHz, 1MHz, or external signal
General purpose 16-bit down counter
GP clock source 10MHz, 100KHz, or external signal