User manual

ATHENA CPU User Manual V1.40 Page 68
0x25E Write WDT Control Register
Bit No. 7 6 5 4 3 2 1 0
Name
WDIEN WDOEN WDSMI WDEDGE
WDIEN 0 = Disable edges on the WDI pin retriggering WDT.
1 = Enable egdes on the WDI pin retriggering WDT.
WDOEN 0 = Disable edge on WDO pin when WDT reaches 1.
1 = Enable edge on WDO pin when WDT reaches 1.
WDSMI 0 = Disable SMI signal when WDT reaches 0.
1 = Enable SMI signal when WDT reaches 0.
WDEDGE 0 = Falling edge on WDI retriggers WDT when WDIEN = 1.
1 = Rising edge on WDI retriggers WDT when WDIEN = 1.
0x25E Read WDT Control Register
Reads back current state of the WDT Control Register.
0x25F Write Chip select enable/disable
Bit No. 7 6 5 4 3 2 1 0
Name
COM4EN COM3EN FPGAEN WDEN
COM4EN COM4 chip select enable. 1 = enable COM4-CS#. 0 = disable COM4-CS#.
COM3EN COM3 chip select enable. 1 = enable COM3-CS#. 0 = disable COM3-CS#.
FPGEN FPGA chip select enable. 1 = enable FPGA-CS#. 0 = disable FPGA-CS#.
WDEN Watchdog enable. 1 = WDT counter enable. 0 = WDT counter disable, WDO
disable, WDI disable, CPURST# disable, EXTSMI# disable.
The CPLD initializes all values to zero on power up. The BIOS then enables each
resource based on BIOS settings.
0x25F Read Chip select enable/disable
Bit No. 7 6 5 4 3 2 1 0
Name
COM4EN COM3EN FPGAEN WDEN
Reads back current state of the chip select values