User manual

ATHENA CPU User Manual V1.40 Page 66
19. WATCHDOG TIMER PROGRAMMING
19.1 Watchdog Timer
Athena contains a watchdog timer circuit consisting of one programmable timer, WDT. The input
to the circuit is WDI, and the output is WDO. Both signals appear on the watchdog connector J6.
WDI may be triggered in hardware or in software. A special “early” version of WDO may be output
on the WDO pin. When this signal is connected to WDI, the watchdog circuit will be retriggered
automatically.
The duration of the timer is user-programmable. When WDT is triggered, it begins to count down.
When it reaches zero, it will generate a user-selectable combination of these events:
♦ System Management interrupt (SMI)
♦ Hardware reset
The watchdog timer circuit is programmed via I/O registers located at address 0x25C. Detailed
programming info can be found below. The Athena watchdog timer is supported in the DSC
Universal Driver software version 5.7 and later.
Address Write Function Read Function
0x25C WDT trigger register None, write only
0x25D WDT, counter register None, write only
0x25E Watchdog control register Readback, see details
0x25F Chip select enable/disable Readbacks the same written bits
Register Map Bit Assignments
A blank bit in the write registers is unused. A blank bit in the read registers reads back as 0 or 1,
unknown state.
WRITE
Address 7 6 5 4 3 2 1 0
0x25C WDTRIG
0x25D WDT3 WDT2 WDT1 WDT0
0x25E WDIEN WDOEN WDSMI WDEDGE
0x25F COM4EN COM3EN FPGAEN WDEN
READ
Address 7 6 5 4 3 2 1 0
0x25C
0x25D
0x25E WDIEN WDOEN WDSMI WDEDGE
0x25F COM4EN COM3EN FPGAEN WDEN
Table 22: I/O COM3/4 Control Register Definition