User manual

ATHENA CPU User Manual V1.40 Page 56
13.1 Athena A/D Operating Modes
The following control bits and values are referenced in the descriptions in the table below.
AINTE Base + 4 bit 0
SCANEN Base + 3 bit 2
FIFO threshold Base + 5 bits 5-0
STS Base + 3 bit 7
LOW, HIGH 4-bit channel nos. in Base + 2
ADCLK Base + 4 bit 4
AINTE SCANEN Operation
0 0 - Single A/D conversions are triggered by write to B+0.
- STS stays high during the A/D conversion.
- No interrupt occurs.
- The user program monitors STS and reads A/D data when it goes low.
0 1 - A/D scans are triggered by write to B+0. All channels between LOW and HIGH
will be sampled.
- STS stays high during the entire scan (multiple A/D conversions).
- No interrupt occurs.
- The user program monitors STS and reads all A/D values when it goes low.
1 0 - Single A/D conversions are triggered by the source selected with ADCLK.
- STS stays high during the A/D conversion.
- A/D interrupt occurs when the FIFO reaches its programmed threshold.
- The interrupt routine reads out a number of samples equal to the FIFO threshold
each time it runs.
1 1 - A/D scans are triggered by the source selected with ADCLK.
- STS stays high during the entire scan (multiple A/D conversions).
- A/D interrupt occurs when the FIFO reaches its programmed threshold.
- The interrupt routine reads out a number of samples equal to the FIFO threshold
each time it runs.
Table 21: A/D Operating Modes